Oracle International Corporation

Novell, Inc.

Clyde R Griffin

Kattiganehalli Y Srinivasan

Ranjan Gupta

Methods and apparatus involve booting a computing device from a flash device. The flash device has memory partitions, including a read-only and a read/write partition. The read-only includes an operating system for use by the computing device and defines an initial system state. The read/write is configured to store a delta from the initial system state. Upon booting the computing device subsequent to an initial boot, the delta and the initial system state together define the whole system state. In other features, a write engine from the read-only partition tracks changes to the initial system state and writes some, but not all of the changes back to the read/write partition thereby minimizing a number of writes to the flash memory. In this manner, the speed of the flash memory can be used to quickly boot/reboot a computing device, while avoiding the wear limits associated with writing to flash devices.

Flash memory device having memory partitions and including an embedded general purpose operating system for booting a computing device

A method for achieving low overhead for operating system (&ldquo;OS&rdquo;) interrupts is described. In a preferred embodiment, when an interrupt occurs, a lightweight interrupt handler is used to acknowledge that the interrupt occurred, prevent the CPU and the OS from fully servicing the interrupt until a designated future time, set a CPU flag indicating that the interrupt has been received, and return from the lightweight interrupt handler. In this manner, the interrupt is partially acknowledged by the CPU and the OS, but the driver that caused the interrupt is still awaiting service. To achieve low latency, a heavyweight (&ldquo;non-deferrable&rdquo;) time-based interrupt that flushes all deferred interrupts is scheduled to occur within a specified time. At a later time, when drivers would normally be polled for work, the CPU flag is checked to see if there is interrupt work. If so, with all interrupts disabled at the CPU, the pending interrupt vectors are unmasked to determine which ones need to be serviced. In one embodiment, this is accomplished by examining a special register in the CPU designated for this purpose. Subsequently, the deferred interrupts are batch processed sequentially by calling their service routines without any context save required.

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Mapleton, UT, United States of America

Clyde R Griffin