Texas Instruments Corporation

Triquint Semiconductors Texas, Inc.

Clyde R Fuller

Joseph B Delaney

John Michael Bedinger

Thomas E Nagle

Robbie W Skinner

Prabhakar Bhimrao Ghate

Robert H Eklund

Timothy S Henderson

Gordon P Pollack

Arthur M Wilson

Victor C Sutcliffe

Pradeep L Shah

Robert C Hooper

Betty S Mercer

Dave Monahan

Neal Jay Tolar

Barry William Battershall

A method, system and materials for use in hydrogen gettering in conjunction with microelectronic and microwave components that are generally hermetically sealed in an enclosure typically referred to as a 'package'. Gettering materials that can be used include titanium with or without a hydrogen permeable coating or covering, alloys of zirconium-vanadium iron and zeolites and several ways to apply these materials to the package. In addition, the hydrogen permeable material can be used over a vent from the interior of the package to the exterior wherein hydrogen will escape from the package interior when the hydrogen concentration within the package is greater than without the package.

Hydrogen gettering system

A method, system and materials for use in hydrogen gettering in conjunction with microelectronic and microwave components that are generally hermetically sealed in an enclosure typically referred to as a &ldquo;package&rdquo;. Gettering materials that can be used include titanium with or without a hydrogen permeable coating or covering, alloys of zirconium-vanadium iron and zeolites and several ways to apply these materials to the package. In addition, the hydrogen permeable material can be used over a vent from the interior of the package to the exterior wherein hydrogen will escape from the package interior when the hydrogen concentration within the package is greater than without the package.

Generally, and in one form of the invention, a method is disclosed for forming an ohmic contact on a GaAs surface,comprising the steps of depositing a layer of InGaAs,over the GaAs surface,, and depositing a layer of TiW,on the layer of InGaAs,, whereby a reliable and stable electrical contact is established to the GaAs surface,and whereby Ti does not generally react with the In.

Method of forming a low-resistance contact on compound semiconductor

Generally, and in one form of the invention, a method is disclosed for forming an ohmic contact on a GaAs surface 20 comprising the steps of depositing a layer of InGaAs 22 over the GaAs surface 20, and depositing a layer of TiW 24 on the layer of InGaAs 22, whereby a reliable and stable electrical contact is established to the GaAs surface 20 and whereby Ti does not generally react with the In.

Low-resistance contact on a compound semiconductor

The disclosure relates to a semiconductor circuit on a single chip, preferably of gallium arsenide, wherein insulating layers with vias therein for receiving metallization include a thin silicon nitride layer beneath a relatively much thicker silicon oxide layer with the nitride exposed on the via side walls to contact gold in the metallization within the via. The disclosure further includes metallization formed as a TiW/Au/TiW sandwich wherein the TiW layer contacting the insulator on the substrate is formed of a first tensile film of TiW with a compressive film of TiW of substantially the same thickness thereover and in contact therewith to lower the tensile force applied by the tensile layer, yet maintain the resultant force tensile.

Semiconductor circuit

Generally, and in one form of the invention a method for making a heterojunction bipolar transistor comprising the steps of forming a compound semiconductor material structure comprised of a plurality of layers, wherein at least one of the plurality of layers is comprised of a first material (e.g. GaAs 36) and at least one of the remaining of the plurality of layers is comprised of a second material (e.g. AlGaAs 32); and etching the layers comprised of the first material with an etchant that does not appreciably etch the layers of the second material is disclosed. A surprising aspect of this invention is that no additional etch stop layer was added in the material structure. Etchants were found that stop on the wide band gap emitter layer (e.g. AlGaAs) usually found in heterojunction bipolar transistors despite the similarity of the materials. An advantage of this method is that a reference point for timing subsequent etches is established at a point other than the top of the uppermost of the layers, thereby improving the accuracy with which the depth of the subsequent etching can be controlled. Improved etch depth accuracy directly relates to more producible and higher yield heterojunction bipolar transistor devices. Other devices, systems, and methods are also disclosed.

Compound semiconductor heterojunction bipolar transistor

A sputter-etch process is used to etch vias having substantially vertical sidewalls, such that a sloped sidewall is formed. Using a silicon dioxide layer in which to form the vias, slopes of approximately 45.degree. may be obtained. A second insulator layer may be provided to protect the leads and other portions of the device during the sputter-etch to prevent damage.

Method of forming a via having sloped sidewalls

Semiconductor circuit having metallization with TiW

Refractory metals, refractory metal silicide, and polysilicon/refractory metal silicide sandwich structures integrated circuits are etched using carbonyl chemistry. That is, the deposited material is plasma etched using an etchant gas mixture which contains a gas, such as CO2, which can dissociate to provide carbonyl groups (CO) or, in combination with halogen sources, carbonyl halide radicals.

Plasma etching of refractory metals and their silicides

A microelectronic integrated circuit having first and second levels of thin-film metallization separated by an insulation layer is provided with a system for electrical interconnections between metallization levels, at selected locations, without requiring extra spacing between metal paths, in either the first or second levels. Maximum circuit density is thereby permitted, with no restriction on the placement of interconnection vias. Circuit layout is greatly simplified because all metal paths have uniform widths and minimum spacings, achieved with the use of vias that are 'oversized' in both the transverse and longitudinal directions. Consequently, it is required that second level metal differ in composition from first level metal, and be patterned with an etchant that does not attack first level metal.

Maximum density interconnections for large scale integrated circuits

Silicon solar cells may be made from either 'P' type substrates with 'N' type dopants to form the geometries or with 'N' type substrates and 'P' type dopants forming the junction. This invention relates to the dopant species employed, the improved method of application and junction formation, formation of insitu anti-reflective coatings, and improved metallization processing for silicon solar cells. The invention does not affect preparation of the silicon substrate prior to diffusion steps, and is applicable both to planar solar cells and to vertical-multijunction cells. This invention discloses an alternate process of junction formation using arsenic as dopant. The process is uniquely different in the fact that it simplifies the number of process steps by using the doped oxide for junction formation, metallization mask and as an anti-reflection surface layer.

Process for fabricating inexpensive high performance solar cells using

The disclosure relates to patterning of platinum effectively and then removing the mask from the platinum without attacking the chromium metal beneath the platinum. If tantalum is used on top, which metal can be patterned with CF.sub.4, the tantalum can be patterned and the platinum can then be patterned quite readily and the tantalum can then be removed with the CF.sub.4 again and then the gold can be plated up onto the platinum patterns and the chromium can then be etched out using conventional chromium etch which will not attack any of the other metals. This solves the problem of high yield patterning with a metal mask and process for patterning and removal of that metal mask that is compatible with the chromium-platinum metal system. The advantage of the chromium-platinum system over the titanium-platinum system is the resistance of the chromium to silicon etch. Therefore, the principal application of this invention would be in the fabrication of mesa devices.

Method of patterning Cr-Pt-Au metallization for silicon devices

A process has been developed for fabricating a nonpolar low loss thin film capacitor utilizing tantalum oxide for high capacitance per unit area as a dielectric which is deposited in film form relative to a suitable substrate. A counter electrode is deposited on a substrate. A film of metal having a high recrystallization temperature is deposited on the counter electrode. This deposition forms the bottom electrode of the capacitor structure. The metal film has a quality thermal expansion resistance and a high reliability in thermal environments.

Growing community of inventors

Plano, TX, United States of America

Clyde R Fuller