General Electric Company

Ericsson Ge Mobile Communications Inc.

Clyde R Butler, Jr

Craig F Szczutkowski

Marc A Dissosway

Gerald M Cooper

A digitally controller radio transceiver includes a housing including a front cover provided with a display port; a main controller board mounted within the housing; an optional display board attached to an interior surface of the front cover adjacent said display port, said display board electrically connected to said main controller board by a pressure fit connection; a removable display escutcheon plate mounted on an exterior surface of the cover, overlying the display port; and fastening means extending through the cover and connecting the display board to the display escutcheon plate. Removal or omission of the display board is automatically sensed by the radio transceiver's internal microprocessor which operates accordingly. In one embodiment the transceiver program store may be loaded via an external connector to customize the microprocessor instruction code for the presence or absence of a display.

Radio transceiver with optional display

Different digital radio transceiver front panel escutcheon plate assemblies are provided for different optional transceiver configurations. A digital signal controller which is part of the main transceiver circuitry is capable of performing any of various basic and option functions under control of program control instructions stored in an associated non-volatile memory. Subsets of those features are selectively disabled by irreversibly modifying the transceiver unit from the outside of the unit (e.g., by cutting certain PC board pathways through holes provided in the transceiver unit front panel). The controller enables (executes) portions of the program control instructions stored in its associated non-volatile memory and disables (does not execute) other portions of the stored program control instructions in response to detection of continuity/discontinuity over those certain pathways.

Method and apparatus for externally defining the operational mode of a

A memory protection arrangement particularly suitable for use with battery backed-up CMOS RAMs. The voltage level of power to the CMOS RAMs is referenced to the logic supply to eliminate latch-up and low voltage problems and to relax the tolerances required in power supply circuits. In addition, the master chip enable for all CMOS RAMs is latched rather than providing a separate latch for individual chip enable. Furthermore, the state of the logic supply is latched at the beginning of each memory cycle to prevent disabling of the CMOS RAMs during a cycle. An additional voltage sensor controls the enable of a buffer for each chip enable.

Growing community of inventors

Lynchburg, VA, United States of America

Clyde R Butler, Jr