Advanced Micro Devices Corporation

Clive Martin Jones

Tim Z Hossain

Amiya R Ghatak-Roy

Jin Zhao

Zhiyong Zhao

Bob Anderson

Ting H Yuan

Various methods of determining ion implant dosage are disclosed. In one aspect, a method of processing a semiconductor workpiece that has a device region and an inactive region is provided. A first mask is formed on a first portion of the inactive region. A first implant of ions is performed on the device region and the first mask. A secondary ion mass spectrometry analysis of the first portion of the first mask is performed to determine a composition thereof relative to a standard composition. A dose for the first implant is determined based upon the secondary ion mass spectrometry analysis of the first portion of the first mask. The first implant dose is compared with a prescribed dose for the first implant to determine if a second implant is necessary to achieve the prescribed dose, and if so, an appropriate make-up dose for the second implant.

Analysis of ion implant dosage

A method of forming conductive interconnections is disclosed herein. In one illustrative embodiment, the method comprises forming an opening in a layer of insulation material, forming a first plurality of silicon seed atoms in the opening, and performing a first tungsten growing process to form tungsten material in the opening. The method further comprises forming a second plurality of silicon seed atoms in the opening above at least a portion of the tungsten material formed during the first tungsten growing process, and performing at least one additional tungsten growing process after forming the second plurality of silicon seed atoms to further form tungsten material in the opening.

Method of forming conductive interconnections on an integrated circuit device

Various methods of fabricating a tungsten conductor structure are provided. In one aspect, a method of fabricating a tungsten conductor structure in an opening in an insulating film is provided that includes forming a titanium nitride film in the opening and heating the a titanium nitride film. The titanium nitride film is exposed to a flow of hydrogen gas and a flow of an inert carrier gas. The titanium nitride film is exposed to a flow of silane at a first flow rate for a first time interval and to a flow of tungsten hexafluoride for a second time interval that begins after the beginning but prior to the end of the first time interval. The flow of silane is reduced at the end of the first time interval to a second flow rate and maintained at the second flow rate for a third time interval. Fluorine diffusion into the titanium nitride film and the potential for void formation due to non-conformal tungsten deposition are reduced.

Two-level silane nucleation for blanket tungsten deposition

Semiconductor structures having dielectric material layers that are below 3 nanometers in thickness can now be measured with greater precision and in less time using a SIMS device. In an example embodiment of the present invention, a method of measuring the thickness of a dielectric material layer of a semiconductor structure formed on a substrate includes directing a high energy ion beam at a portion of the substrate and sputtering off a plurality of targeted ions from the substrate. The thickness of the dielectric material layer is then determined as a function of a dosage level of the targeted ion and a density of the targeted ion in the dielectric material.

Method of measuring dielectric layer thickness using SIMS

A transistor and a method for making a transistor are described. A silicon gate conductor is patterned over a gate dielectric upon a silicon substrate. Dopant impurity distributions self-aligned to the gate conductor may be introduced. Silicon nitride (&ldquo;nitride&rdquo;) spacers are formed adjacent to opposed sidewall surfaces of the gate conductor. Oxide caps are formed covering exposed outer surfaces of the nitride spacers. The oxide caps prevent dissociation of the nitride spacers during a subsequent pre-amorphization implant. A preclean is subsequently used to remove oxides from the surfaces of the gate conductor and semiconductor substrate. The preclean may also remove the oxide caps, but does not attack the nitride spacers. A salicide process is used to form low-resistance gate, source, and drain silicides. The presence of nitrogen in the nitride spacers is believed to help prevent dopant outdiffusion from adjacent silicon, prevent silicide bridging across spacers, and increase resistance of the spacers to oxide etchants.

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Austin, TX, United States of America

Clive Martin Jones