Texas Instruments Corporation

Clive D Bittlestone

Srinath Mathur Ramaswamy

Joyce Kwong

Manish Goel

Yuming Zhu

Kevin M Ovens

Sai Zhang

Chiraag Juvekar

Anand Ganesh Dabak

Anuj Batra

Bryan David Sheffield

Srinivas Lingam

Francisco A Cano

Uri Weinrib

Dharin Nayeshbhai Shah

Barak Cherches

Stephen Keith Heinrich-Barna

Girishankar Gurumurthy

Ekanayake Ajith Amerasekera

David A Thomas

Brian D Borchers

Bob Helmick

Kit Wing S Lee

Steven P Korson

Doug Counce

Shivaling S Mahant-Shetti

Uming U Ko

Donald Edward Steiss

Stephanie Watts Butler

Vipul Kumar Singhal

Robert J Landers

Sumanth Katte Gururajarao

Rolf Lagerquist

Robert C Martin

Kenneth Michael Butler

Mark E Mason

Yunchen Qiu

Peter Cumming

Christopher Barr

Senthil Kumar Sundaramoorthy

Pavan Vithal Torvi

Graham McLeod Barr

Jay Maxey

Systems and methods for validating operation of a software sequence may include: monitoring signals on a bus of a processor, comparing the contents of the signals on the bus to pre-stored information from compile time. If the comparing generates a match, that may indicate that the software sequence is operating as intended. However, if the comparing generates a mismatch, that may indicate that the software sequence is not operating as intended and may, in fact, indicate a malicious use. Further actions can be taken in response to a mismatch, including resetting a processor, issuing an interrupt, and the like.

Systems and methods for monitoring an instruction bus

A method includes programming first and second values and a first compare enable command into respective first operand, second operand, and first compare enable command registers in a hardware comparator circuit. The method includes determining that a first match exists corresponding to the first and second values, programming a third value into the first operand register and a fourth value into the second operand register, and programming a second compare enable command into a second compare enable command register in the hardware comparator circuit. In response to a determination that a second match exists corresponding to the third and fourth values, the method includes asserting a success interrupt signal, programming a fifth value into the first operand register and a sixth value into the second operand register and programming a second compare enable command into a second compare enable command register in the hardware comparator circuit.

Countermeasure against fault injection attacks

Methods and apparatus for creating a physically unclonable function for SRAM are disclosed. An example method includes decreasing a supply voltage of a memory array to a first voltage level, the first voltage level being below a normal operating voltage associated with the memory array, reading a first value of a bit cell after the supply voltage has been at the first voltage level, and determining a function based on the first value of the bit cell and a second value, the second value stored in the bit cell when the memory array is operating at a voltage level above the first voltage level, the function to represent an identification of a circuit including the memory array.

Methods and apparatus to create a physically unclonable function

A flow meter ultrasonically measures fluid velocity in a pipe and ultrasonically transmits fluid flow data along the pipe. An ultrasonic transducer used for fluid velocity measurement may optionally also be used for communication of flow data, and optionally, the ultrasonic frequency for fluid velocity measurement may be the same as the ultrasonic frequency for communication of flow data.

Ultrasonic flow meter

A system for error correction code (ECC) management of write-once memory (WOM) codes includes, for example, a controller for selecting between one of a WOM (Write-Once Memory) mode and an ECC (error correction code) mode. A codec is arranged to operate in the selected mode. The codec while operating in the ECC mode is arranged to identify a bit position of at least one bit error in response to ECC parity bits of a first received data word. The codec while operating in the WOM mode is arranged to receive a WOM-encoded word from an addressed location in a WOM device, to receive a second received data word to be encoded and written to the addressed location, and to generate WOM-encoded word for writing to the addressed location in the WOM device. The WOM-encoded word for writing to the addressed location is optionally ECC encoded.

Dual-mode error-correction code/write-once memory codec

Read-only ('RO') data consisting of a physically unclonable function ('PUF') pattern is written to a ferroelectric random-access memory (&#x201c;FRAM&#x201d;) memory array. The FRAM array is baked to imprint the PUF pattern with a selected average depth of imprint and a corresponding average read reliability. The average depth of imprint and corresponding average read reliability are determined during testing after baking. The PUF pattern as read after baking is compared to the PUF pattern as written prior to baking. Additional PUF pattern writing and baking cycles may be performed until the average depth of imprint and associated read reliability reach a first selected level. Integrated circuits determined to be over-imprinted by exceeding a second selected level may be rejected. The first and second levels of PUF pattern imprint are selected such as to produce FRAM arrays with a unique fingerprint for each individual FRAM array-containing integrated circuit.

Dual mode memory array security apparatus, systems and methods

Disclosed embodiments include an electronic device having a write-once memory (WOM) and a memory controller. The memory controller includes a host interface receiving a data word including first and second symbols, each having at least two bits, a WOM controller that encodes the first and second symbols and outputs a WOM-encoded word including first and second WOM codes corresponding to the first and second symbols, respectively, an error correction code (ECC) controller that encodes the WOM-encoded word and outputs an ECC-encoded word including the first and second WOM codes and a first set of ECC bits corresponding to a first write operation, and a memory device interface that writes the ECC-encoded word the WOM device in the first write operation. Each of the first and second WOM codes include at least three bits with at least two of the at least three bits having the same logic value.

Error correction code management of write-once memory codes

Methods and apparatus for creating a physically unclonable function for SRAM are disclosed. An example method includes after applying a voltage to a memory array: determining a first duration between the applying of the voltage and a first output of a first bit cell, the first output corresponding to a first value stored in the first bit cell, and determining a second duration between the applying of the voltage and a second output of a second bit cell, the second output corresponding to a second value stored in the second bit cell. The example method further includes determining a function based on a comparison of the first duration and the second duration, the function to establish an identification of a circuit that includes the memory array.

Apparatus and method for physically unclonable function (PUF) for a memory array

A memory area is protected from rowhammer attacks by placing an extra sacrificial row at the top and the bottom of the memory addresses defining the area to be protected. The sacrificial rows of memory are written with a known bit pattern that may be read periodically to detect any rowhammer attacks that may be in progress.

Bitflip security attack protection

Apparatus for physically unclonable function (PUF) for a memory array

A system for error correction code (ECC) management of write-once memory (WOM) codes includes, for example, a host processor is arranged to send a data word that is to be stored in a WOM (Write-Once Memory) device. A host interface is arranged to receive the first data word for processing by a WOM controller and an ECC controller. The WOM controller is for generating a first WOM-encoded word in response to an original symbol of the first data word, while the ECC controller is for generating a first set of ECC bits in response to the original symbol of the first data word. A memory device interface is for writing the first WOM-encoded word and the first set of ECC bits to the WOM device in accordance with the memory address associated with the first data word.

A system for write-once memory (WOM) code emulation of EEPROM-type devices includes, for example, a host processor for sending data words for storing in a WOM (Write-Only Memory) device. A host interface receives the data words for encoding by a WOM controller. An emulator programs the WOM-encoded data and an address identifier as an entry of the WOM device. The emulator overwrites previously programmed WOM-encoded data by searching entries of a current active page of a WOM device to locate a programmed WOM entry that includes the searched-for address identifier and the previously written WOM-encoded data word. When the previously written WOM-encoded word cannot be correctly overwritten, the contents of the second WOM-encoded word are stored in a new entry. When the current active page is substantially full, the new entry is stored a new page and the current active page is block-erased.

WOM code emulation of EEPROM-type devices

Growing community of inventors

Allen, TX, United States of America

Clive D Bittlestone