International Business Machines Corporation

Clive A Collins

Dale E Pontius

David B Rolfe

Christine M Desnoyers

Billy J Knowles

Vincent F Sollitto

The sense amplifier registers (SARs) servicing the arrays of a dynamic random access memory (DRAM) located on a semiconductor chip with a processor are all maintained at full power while unaccessed arrays are powered down to conserve power. Accessing circuits for the DRAM permit accessing by the processor of word length segments of each of the SARs independently of one another so that the SARs function as a read/write cache for the processor.

Dynamic random access memory persistent page implemented as processor

An automatic clock tuning and measuring system is provided for data processing system wherein fixed frequency clock pulses are selectively delayed and distributed in accordance with a clock path and delay selection made by a computing means. A reference generator is connected to the fixed frequency clock pulses source for delaying the clock pulses a reference amount which is selected by the computing means in accordance with the predetermined delay associated with the selected path. An automatic time measuring means is connected to both the reference generator and the clock distribution means for providing an output indicative of the time comparison condition of a delayed clock pulse and the reference delayed clock pulse. The output time comparison or non-comparison of the delayed clock pulse and the reference delayed clock pulse is utilized through the computer means to adjust the amount of delay introduced by the automatic delay means or is utilized to adjust the delay increment established in the reference generator to provide the clock tuning and measuring respectively.

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Wappingers Falls, NY, United States of America

Clive A Collins