Achronix Semiconductor Corporation

Clinton W Kelly

Rajit Manohar

Virantha N Ekanayake

Raymond Nijssen

Christopher C LaFrieda

Marcel Van Der Goot

Gael Paul

Kamal Chaudhary

Ilya K Ganusov

Hong Tam

Circuits comprising an asynchronous programmable interconnect with fan out support that include a multi-port switch and a first and second buffer-switch circuit, and methods of forming such circuits, are provided. Additional circuits and methods are disclosed.

Asynchronous pipelined interconnect architecture with fanout support

In accordance with the present invention there are provided herein asynchronous reconfigurable logic fabrics for integrated circuits and methods for designing asynchronous circuits to be implemented in the asynchronous reconfigurable logic fabrics.

Reconfigurable logic fabrics for integrated circuits and systems and methods for configuring reconfigurable logic fabrics

Methods, systems, and circuits that implement timing analyses of an asynchronous system are described. A method may include converting a synchronous circuit design into an asynchronous representation, wherein a critical path may be identified. The critical path may be converted to a corresponding path in the synchronous circuit design. Additional methods, systems, and circuits are disclosed.

Asychronous system analysis

Circuits comprising asynchronous linear pipelines and one-phase pipelines, and methods of forming asynchronous linear pipeline circuits and converting them to one-phase pipeline circuits are provided. Additional circuits, systems and methods are disclosed.

One phase logic

Methods, circuits, and systems for converting reset mechanisms in a synchronous circuit design into a corresponding asynchronous representation are described. These may operate to convert synchronous state holding blocks that include reset signals to corresponding asynchronous dataflow logic blocks. A replicated reset token at a fraction of the operational frequency of the reset signal may be distributed to the locations of the asynchronous dataflow logic blocks. Additional methods, circuits, and systems are disclosed.

Reset mechanism conversion

Methods, systems, and circuits for implementing multi-clock designs in asynchronous logic circuits are described. A method may include associating one or more data tokens with a clock domain of a multi-clock domain netlist. A durational relationship between a clock period associated with the clock domain and one or more other clock domains of the multi-clock domain netlist may be determined. Data tokens used in other clock domains may be transformed based on the determined relationship.

Multi-clock asynchronous logic circuits

Methods, systems, and circuits for forming and operating a crossbar structure in an asynchronous system are described. One or more input ports of a programmable crossbar structure may be connected to send data to one or more output ports. A group of output ports each receiving data from an input port may be connected to send, in response, control signals via a programmable element to the input port. The number of programmable elements used may be determined by the number of input ports being copied to more than one output port. Additional methods, systems, and circuits are disclosed.

Programmable crossbar structures in asynchronous systems

A synchronous circuit design is converted to an asynchronous circuit by converting synchronous circuit logic to an asynchronous circuit logic, and one or more additional tokens into the converted asynchronous circuit. The circuit is initialized with a desired additional number of tokens placed in the asynchronous circuit, or a desired number of tokens are inserted at an input before taking tokens from an output.

Token enhanced asynchronous conversion of synchonous circuits

New and improved methods and circuit designs for asynchronous circuits that are tolerant to transient faults, for example of the type introduced through radiation or, more broadly, single-event effects. SEE-tolerant configurations are shown and described for combinational logic circuits, state-holding logic circuits and SRAM memory circuits.

Fault tolerant asynchronous circuits

Methods, circuits and systems for converting of a non-predicated asynchronous netlist to a predicated asynchronous netlist are described. These may operate to identify one or more portions of an asynchronous netlist corresponding to a partially utilized portion of an asynchronous circuit. The asynchronous netlist may be modified to control the partially utilized portion. Additional methods, circuits, and systems are disclosed.

Growing community of inventors

San Jose, CA, United States of America

Clinton W Kelly