Lsi Logic Corporation

Clinton P Seeman

Danny C Vogel

Bryan Robb

Victor Helenic

An integrated circuit comprising a plurality of link layer controllers. The plurality of link layer controllers may be configured to operate independently in a first mode and cooperatively in a second mode.

High speed OC-768 configurable link layer chip

An apparatus comprising a media access controller (MAC), a configurable packet switch, and a network protocol stack in silicon. The network protocol stack may be configured to couple the media access controller to the configurable packet switch.

High speed network protocol stack in silicon

In a Framed Packet Bus (FPB) serial bus, an improved protocol and circuit layout for communication between devices grounded in the same chassis or chip. The improved protocol eliminates the requirement that bits have DC balance in their HIGH and LOW voltage levels. Consequently, bus overhead is reduced over prior techniques. In one example, data capacity utilization was increased from 80% to 95% and bus overhead was reduced from 20% to 5%. As a result of increased capacity, more packets of data may be carried across the serial bus, and any leftover bits within the frame cycle and in subsequent cycles may carry error detection information or be utilized as a control for the bus. In one preferred embodiment, the FPB serial bus configuration consists of sixteen serial lines arranged in parallel.

Growing community of inventors

Blackstone, MA, United States of America

Clinton P Seeman