International Business Machines Corporation

Clinton E Bubb

John R Flanagan

Daniel Francis Casper

Raymond Michael Higgs

Howard M Haynie

Michael Grassi

Kirk D Pospesel

George Kuch

Jeffrey M Turner

Andrew R Ranck

Luke M Hopkins

Ying-Yeung Li

Gabriel Martel Tarr

Michael James Becht

Myron Wisniewski

Enrique Aleman

Carl Alfred Bender

Jie Zheng

Jeffrey C Hanscom

Ralf Winkelmann

Mushfiq U Saleheen

Raymond Wong

Roopesh Ambalath Matayambath

Steven George Aden

Andreas Kohler

Chaitanya Kancherla

Systems and techniques for performing processor debugging over an internal interconnect fabric are described. An example techniques includes obtaining interconnect fabric traffic comprising one or more debugging commands for a first processor within a computing system. The interconnect fabric traffic with the one or more debugging commands is converted into debugging traffic with the one or more debugging commands. The debugging traffic is routed to a debug port of the first processor.

Processor debugging over an interconnect fabric

Aspects of the present invention include a method, system and computer program product. The method includes a processor operating first and second physical channel identifier (PCHID) devices comprised of a plurality of functional logic components, wherein one or more of the functional logic components are specific to one or more of the first and second PCHIDs and wherein one or more of the functional logic components are in common and not specific to one or more of the first and second PCHIDs; determining that an error condition exists in the first PCHID or the second PCHID; and executing a recovery method to remove the error condition from the first PCHID or the second PCHID in which the error condition exists.

Dual physical-channel systems firmware initialization and recovery

A system for managing one or more queues in a multi-processor environment includes a shared memory configured to be accessed by a plurality of processing elements, and a queue manager configured to control a queue in the shared memory, the queue manager storing dynamically configurable queue parameters including an operation address associated with the queue, a number of queue elements and a size of each queue element. The queue manager is configured to intercept a message from a processing element, the message directed to the shared memory and specifying the operation address, calculate an address of a location in the shared memory corresponding to one or more available queue elements, the calculating performed based on the operation address, the number of queue elements, and the size of each queue element, and perform one or more queuing operations on the queue based on the calculated address.

Configurable hardware queue management and address translation

A system for managing one or more queues in a multi-processor environment includes a memory configured to be accessed by a plurality of processing elements, and a queue manager disposed in communication with a plurality of processors and with the memory, the queue manager configured to control a queue in the memory, the queue including a plurality of queue elements, the queue manager configured to intercept a message from a processing element of the plurality of processing elements and perform one or more queuing operations on the queue based on the message. The system also includes a dynamically configurable queue full value maintained by the queue manager, the queue full value being a threshold value that specifies a maximum number of the queue elements that can be written to before a queue full condition is detected, the maximum number based on a number of processing elements.

Hardware queue manager with water marking

Aspects of the present invention include a method, system and computer program product. The method includes a processor operating first and second physical channel identifier (PCHID) devices comprised of a plurality of functional logic components, wherein one or more of the functional logic components are specific to one or more of the first and second PCHIDs and wherein one or more of the functional logic components are in common and not specific to one or more of the first and second PCHIDs; determining that an error condition exists in the first PCHID or the second PCHID; executing a recovery method to remove the error condition from the first PCHID or the second PCHID in which the error condition exists; and executing, by the processor, an initialization method for both of the first and second PCHIDs.

A system for managing one or more queues in a multi-processor environment includes a queue manager disposed in communication with a plurality of processors and a memory shared by the plurality of processors, and a queue configured to be controlled by the queue manager, the queue including independent and discrete queue elements and having a starting location specified by a base address, the queue manager having one or more dynamically configurable parameters, the one or more dynamically configurable parameters including a size of each of the queue elements. The queue manager is configured to perform receiving a message from a processor of the plurality of processors, the message including an operation address specifying a fixed storage location in the memory and a request related to accessing the memory, selecting the queue based on the operation address, and performing a queuing operation on the queue based on the request.

Configurable hardware queue management

Examples of techniques for transparent north port recovery of an error in an input/output device are disclosed. In one example implementation according to aspects of the present disclosure, a computer-implemented method may include: detecting, by a processing device, a command timeout; sending, by the processing device, an input/output (I/O) error signal to a host processing system connected to the hardware device via a north port of the hardware device; terminating, by the host processing system, a link between the north port of the hardware device and the host processing system; enabling, by the processing device, halt command forwarding on the hardware device; halting, by the processing device, commands upon detecting the halt command forwarding; and resetting, by the processing device, the link between the north port of the hardware device and the host processing system.

Transparent north port recovery

A method, computer program product, and system to implement access control from a master device to a slave device over an inter-integrated circuit (I2C) interface are described. The method includes generating, using a processor, a control block defining the access control to the slave device over the I2C interface. The generating the control block is performed by the trusted code layer and the generating the control block is prohibited by the user-modifiable code layer. The method also includes controlling a command over the I2C interface to the slave device based on a generated command from the trusted code layer and the user-modifiable code layer in accordance with the control block.

Access and protection of I2C interfaces

Processing of out-of-order data transfers is facilitated in computing environments that enable data to be directly transferred between a host bus adapter (or other adapter) and a system without first staging the data in hardware disposed between the host bus adapter and the system. An address to be used in the data transfer is determined, in real-time, by efficiently locating an entry in an address data structure that includes the address to be used in the data transfer.

Facilitating processing of out-of-order data transfers

A computer program product is provided for performing input/output (I/O) processing. The computer program product is configured to perform: generating and storing in local channel memory at least one address control word (ACW) specifying one or more host memory locations for data transfer and including a data discard field; generating an address control structure specifying a local channel memory location of a corresponding ACW; receiving one or more data transfer requests from a network interface that each corresponding address control structure information; accessing an ACW and routing the data transfer request to a host memory location specified in the ACW; and responsive to encountering an error during at least one of the accessing and the routing, discarding the one or more data transfer requests and setting the data discard field to a value configured to instruct a channel to discard any subsequent data transfer requests associated with the ACW.

Fibre channel input/output data routing including discarding of data transfer requests in response to error detection

A method of performing an input/output (I/O) processing operation includes: generating an address control structure for each of a plurality of consecutive data transfer requests, each address control structure specifying a local channel memory location of a corresponding address control word (ACW); receiving a data transfer request from a network interface that includes addressing information specified by a corresponding address control structure; comparing, by a data router in the channel, an Offset field of an address control structure and an Expected Offset field of an ACW to determine whether the data transfer request has been received in the correct order; and based on determining that the data transfer request has been received in the correct order, accessing the ACW by the data router and routing the data transfer request to a host memory location specified in the ACW.

Growing community of inventors

Pleasant Valley, NY, United States of America

Clinton E Bubb