Motorola Corporation

Other

Clinton C Kuo

Ko-Min Chang

Bruce L Morton

Ernest A Carter

Keith E Witek

Thomas R Toms

Kent J Cooper

Mark S Weidner

Henry Y Choe

Thomas Jew

Ming-Bing Chang

David W Chrudimsky

Joseph Jelemensky

Philip S Smith

Horst Leuschner

Ning Hsieh

Sam Dehganpour

Ann E Harwood

Yoshiko K Inoue

A floating-gate non-volatile memory (30) uses a relatively-low threshold voltage to define a programmed state. The memory (30) compensates for fast program cells by providing program pulses which increase in length and magnitude while the cells are being programmed. Between each program pulse the memory (30) determines whether selected cells have been adequately programmed. The memory (30) ceases applying the series of pulses to each cell when it has been adequately programmed. Thus the memory (30) avoids the over-program condition instead of compensating for it.

Non-volatile memory with over-program protection and method therefor

A memory circuit and method of formation uses a transmission gate (24) as a select gate. The transmission gate (24) contains a transistor (30) which is an N-channel transistor and a transistor (28) which is a P-channel transistor. The transistors (28 and 30) are electrically connected in parallel. The use of the transmission gate (24) as a select gate allows reads and writes to occur to a memory cell storage device (i.e. a capacitor (32), a floating gate (22), etc.) without a significant voltage drop occurring across the transmission gate. In addition, EEPROM technology is more compatible with EPROM/flash technology when using a transmission gate as a select gate within EEPROM devices.

Static random access memory cell having a thin film transistor (TFT)

Memory cell having a plural transistor transmission gate and method of

A process for fabricating an improved nonvolatile memory device includes the formation of a control gate electrode (70) which overlies a floating gate electrode (42) and is separated therefrom by an inter-level-dielectric layer (62). The control gate electrode (70) and the underlying floating gate electrode (42) form a stacked gate structure (72) located in the active region (44) of a semiconductor substrate (40). An electrically insulating sidewall spacer (54) is formed at the edges of the floating gate electrode (42) and electrically isolates the control gate (70) from the semiconductor substrate (40). During the fabrication process, implanted memory regions (56, 58) are formed in the active region (44) prior to the formation of control gate electrode (70). A word-line (68) and the control gate (70) are formed by anisotropic etching of a semiconductor layer (66), which is deposited to overlie inter-level-dielectric layer (62). During the etching process, inter-level-dielectric layer (62) prevents the removal of surface portions of semiconductor substrate (40).

Nonvolatile memory process

A static RAM includes test features which provide for the detection of soft defects which may cause a defective SRAM cell to behave as a functional DRAM cell. Provision is made for writing either a high or a low logic state to each bit line of the SRAM while not writing any value to its complementary bit line and for sensing the state of each bit line independently of the state of its complementary bit line. In addition, a current test is provided which detects soft defects by means of the increased inverter leakage current caused thereby. It is possible, by properly combining these tests, to reliably detect all soft defects, thereby assuring the data retention capability of the SRAM. This technique avoids the long hold time and/or high temperature test techniques used in the prior art.

Static RAM with test features

A flash EEPROM array (22) is erased and a threshold voltage distribution of the erased flash EEPROM cells (36, 39-46) is converged to within a predetermined voltage range by using a two-step erasing procedure. In the first step, flash EEPROM array (22) is electrically bulk erased using a conventional bulk erase procedure. Electrons are tunneled from the floating gate (38) to the source, causing cells (36, 39-46) to have a relatively low threshold voltage. In the second step, the threshold voltage distribution of the array (22) is converged to within the predetermined voltage range by grounding the source and drain of each cell (36, 39-46), while concurrently applying a high positive voltage to the control gate (27) of each cell (36, 39-46). Some electrons are tunneled back to the floating gate (38), thus converging the threshold voltage distribution to within a predetermined range.

Apparatus and method for erasing a flash EEPROM

A block erasable flash EEPROM (22) having a single array (68) which can be partitioned into one or more blocks (50-57). The same column decode/block select circuitry (66) is used to provide both column select signals (71) and block select signals (73). The number of blocks (50-57) and the size of each block (50-57) can be determined by the manufacturer during the manufacturing process. Each block (50-57) has a corresponding charge pump (80-87). Each charge pump (80-87) is capable of erasing a single block within the array (68). Each charge pump (80-87) has a variable capacitor (90-97). Each of the variable capacitors (90-97) can be sized according to the size of its corresponding block (50-57).

Block erasable flash EEPROM apparatus and method thereof

An EEPROM cell (10) has a tunnel opening (28) which overlaps both an active region (12) and field isolation regions (14). A tunnel area (30), which is that portion of the cell in which electrons tunnel through a tunnel dielectric (32) to charge or discharge a floating gate (22) during device operation, is defined as the overlapped portion of the tunnel opening (28) and the active region (12). By having the tunnel opening (28) larger than the tunnel area (30), etch processes used to pattern the opening in a gate dielectric (26) are more easily controlled and the active region area beneath the floating gate is reduced. The EEPROM cell (10) has a tunnel area which is limited in size by lithographic resolution capabilities rather than by limitations in dielectric etch processes. The tunnel features increase a capacitance coupling ratio of the cell.

Process for fabricating an EEPROM cell having a tunnel opening which

A bias voltage generator (12) provides a bias control voltage that is connected to a gate of transistor (32) to sink a predetermined amount of bias current. The bias voltage generator (12) is also connected to a gate of a transistor (31) to limit the voltage to a selected bit-line within an array of flash EEPROM cells (26). The predetermined bias current is summed with the current from a selected flash EEPROM cell (46). A reference current generator portion (22), establishes both a reference current and a reference voltage at a second input to a differential amplifier (35). A current-voltage (I-V) characteristic curve of the reference voltage at the second input of the differential amplifier is approximately symmetrically located between the I-V characteristic curves of a flash EEPROM cell when the logic state of the flash EEPROM cell is in an erased state and a programmed state.

Bias current generator circuit for a sense amplifier

A floating gate is utilized which has two portions. A first portion overlies the channel region formed between the source and drain. The control gate overlies this portion of the floating gate and the remaining portion of the channel region forming an enhancement transistor. The second portion of the floating gate extends from the first portion over a thin oxide tunnel area of the source. An additional diode implant forming a junction with the drain region is provided to regulate the current flow through the drain, particularly during erasure.

Nonvolatile memory cell

Zener diodes that are formed concurrently with flash EEPROM cells are utilized to regulate programming voltages for programming a flash EEPROM cell (37). A selected bit-line (38) is voltage regulated with both a zener diode (19) and a bias transistor (36). The bias transistor is activated during programming to prevent breaking down a drain junction of a flash EEPROM cell, which would generate hot-electrons and cause a runaway programming problem. The regulated voltage on the bit-line is also utilized to optimize programming characteristics of a flash EEPROM cell, and to minimize disturbing a programmed logic state of flash EEPROM cells connected to a commonly selected bit-line. A separate zener diode (17) provides a regulated voltage for a selected word-line (40) during programming. By regulating the voltage of the word-line during programming, a program disturb problem associated with a high voltage word-line is minimized.

Zener regulated programming circuit for a nonvolatile memory

Static RAM with soft defect detection

A memory has a programmable circuit which allows a user to select an amount of redundancy the memory has varying from zero percent to one-hundred percent. A received address is compared by the circuit with a redundancy percentage control signal to determine if the address falls within a redundant portion of the memory. If so, a redundancy enable signal is asserted to allow the memory to utilize the redundant circuitry.

User programmable redundant memory

A single transistor EEPROM cell utilizes a tunneling oxide erase mechanism in which the tunneling oxide overlies a portion of the channel region. In addition, an array of single transistor EEPROM cells having a layout which provides convenient byte-at-a-time erase and program operation is disclosed. Two bytes of the array along adjacent rows share a common source, which also forms the source of a pair of erase select transistors, one for each byte. The word lines/control gates of the two bytes form the gates of the two erase select transistors.

Single transistor cell for electrically-erasable programmable read-only

A single transistor EEPROM cell comprises a source, a channel, a drain, a floating gate and a control gate. The control gate and the floating gate are co-extensive over the channel. Programming is achieved by charge injection from the channel and erasing is achieved by tunneling to the source. An array organization is disclosed which features a source/erase control line shared between two adjacent rows of the array, providing efficient byte-at-a-time erasing. An erasure scheme is disclosed which involves repetitive erase pulse-read-erase pulse cycles together with means for assuring complete erasure while preventing over-erasure from driving any cell in the array into depletion mode.

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Austin, TX, United States of America

Clinton C Kuo