Texas Instruments Corporation

Clint Montgomery

Jiong-Ping Lu

Haowen Bu

Lindsey H Hall

John Paul Campbell

Alfred J Griffin, Jr

Adel El Sayed

Mark R Visokay

Brian Keith Kirkpatrick

Freidoon Mehrad

Shaofeng Yu

Scott David Johnson

Ping Jiang

Duofeng Yue

Donald S Miles

Aaron L Frank

Brian M Trentman

David Gonzalez, Jr

Randall W Pak

Vivian Liu

Thomas D Bonifiield

The present invention provides a semiconductor device, a method of manufacture therefor, and an integrated circuit including the semiconductor device. The semiconductor device, among other elements, includes a recrystallized polysilicon layerlocated over a gate electrode layer, a capacitorlocated on the recrystallized polysilicon layer. The capacitor, in this embodiment, includes a first electrode, an insulatorlocated over the first electrode, and a second electrodelocated over the insulator

Capacitor formed on a recrystallized polysilicon layer

One embodiment relates to a method of fabricating an integrated circuit. In the method, p-type polysilicon is provided over a semiconductor body, where the p-type polysilicon has a first depth as measured from a top surface of the p-type polysilicon. An n-type dopant is implanted into the p-type polysilicon to form a counter-doped layer at the top-surface of the p-type polysilicon, where the counter-doped layer has a second depth that is less than the first depth. A catalyst metal is provided that associates with the counter-doped layer to form a catalytic surface. A metal is deposited over the catalytic surface. A thermal process is performed that reacts the metal with the p-type polysilicon in the presence of the catalytic surface to form a metal silicide. Other methods and devices are also disclosed.

Methods for full gate silicidation of metal gate structures

The present invention substantially removes dry etch residue from a dry plasma etch processprior to depositing a cobalt layeron silicon substrate and/or polysilicon material. Subsequently, one or more annealing processesare performed that cause the cobalt to react with the silicon thereby forming cobalt silicide regions. The lack of dry etch residue remaining between the deposited cobalt and the underlying silicon permits the cobalt silicide regions to be formed substantially uniform with a desired silicide sheet and contact resistance. The dry etch residue is substantially removed by performing a first cleaning operationand then an extended cleaning operationthat includes a suitable cleaning solution. The first cleaning operation typically removes some, but not all of the dry etch residue. The extended cleaning operationis performed at a higher temperature and/or for an extended duration and substantially removes dry etch residue remaining after the first cleaning operation

Process method to facilitate silicidation

The present invention provides a method for manufacturing a semiconductor device, and a method for manufacturing an integrated circuit including the semiconductor devices. The method for manufacturing a semiconductor device () , among other steps, includes forming a gate structure () over a substrate () and forming source/drain regions () in the substrate () proximate the gate structure (). The method further includes subjecting the gate structure () and substrate () to a dry etch process and placing fluorine in the source/drain regions to form fluorinated source/drains () subsequent to subjecting the gate structure () and substrate () to the dry etch process. Thereafter, the method includes forming metal silicide regions () in the gate structure () and the fluorinated source/drains ().

Method for manufacturing a semiconductor device having silicided regions

A multilevel metal and via structure is described. The metal conductors include a base or seed layer, a bulk conductor layer, a capping layer, and a barrier layer, and the via structure include a seed layer, a diffusion barrier layer and a metal plug. The via seed layer is controlled to a thickness that discourages the reaction between the via seed layer and the bulk conductor layer. The reaction may result in the formation of harmful voids at the bottom of the vias and is caused by having the via seed metal coming in contact with the bulk conductor through openings in the barrier layer.

Method for forming a void free via

The present invention provides a semiconductor device, a method of manufacture therefor, and a method for manufacturing an integrated circuit. The semiconductor device (), among other possible elements, includes a silicided gate electrode () located over a substrate (), the silicided gate electrode () having gate sidewall spacers () located on sidewalls thereof. The semiconductor device () further includes source/drain regions () located in the substrate () proximate the silicided gate electrode (), and silicided source/drain regions () located in the source/drain regions () and at least partially under the gate sidewall spacers ().

Semiconductor device having a fully silicided gate electrode and method of manufacture therefor

The present invention provides a process of manufacturing a semiconductor device that comprises a process of manufacturing a semiconductor device that includes plasma etchingthrough a patterned hardmask layerlocated over a semiconductor substratewherein the plasma etching forms a modified layeron the hardmask layer, and removing at least a substantial portion of the modified layerby exposing the modified layerto a post plasma clean process.

Post plasma clean process for a hardmask

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Coppell, TX, United States of America

Clint Montgomery