Seagate Technology Incorporated

Lsi Corporation

Agere Systems Inc.

Clifton James Williamson

Erich Franz Haratsch

Johnson Yen

Andrei Vityaev

Victor A Krachkovsky

Milos Ivkovic

Harley F Burger, Jr

Peter Igorevich Vasiliev

Nenad Miladinovic

Venkata Raja Gosula

Schweiray Joseph Lee

Bernardo Rub

Jonathan James Ashley

Jimmie Ray Shaver

Robert D Cronch

Kenneth R Burns

Gary W Reininga

Jonathan Harrington Ormsby

Frank Dwight Willems

Srinivas Maddali

Wuping Chen

Kavi Alptekin

Methods and apparatus are provided for storing data in a multi-level cell flash memory device with cross-page sectors, multi-page coding and per-page coding. A single sector can be stored across a plurality of pages in the flash memory device. Per-page control is provided of the number of sectors in each page, as well as the code and/or code rate used for encoding and decoding a given page, and the decoder or decoding algorithm used for decoding a given page. Multi-page and wordline level access schemes are also provided.

Methods and apparatus for storing data in a multi-level cell flash memory device with cross-page sectors, multi-page coding and per-page coding

Methods and apparatus for soft data generation for memory devices using decoder performance feedback. At least one soft data value is generated in a memory device, by obtaining performance feedback from a decoder; obtaining an error statistic based on the performance feedback; and generating the at least one soft data value based on the obtained error statistic. The performance feedback comprises one or more of decoded bits, a number of erroneous bits based on data decoded by the decoder and a number of unsatisfied parity checks.

Methods and apparatus for soft data generation for memory devices using decoder performance feedback

Methods and apparatus are provided for soft data generation for memory devices. At least one soft data value is generated for a memory device, by obtaining at least one hard read value; and generating the soft data value associated with the at least one hard read value based on statistics for reading the hard read value. The hard read value may be one or more of data bits, voltage levels, current levels and resistance levels. The generated soft data value may be one or more of (i) a soft read value that is used to generate one or more log likelihood ratios, and (ii) one or more log likelihood ratios. The statistics comprise one or more of bit-based statistics and cell-based statistics. The statistics may also optionally comprise pattern-dependent disturbance of at least one aggressor cell on the target cell, as well as location-specific statistics. At least one soft data value can be generated for a memory device, by obtaining a soft read value; and generating the soft data value associated with the soft read value based on statistics for reading the soft read value, wherein the statistics comprise one or more of location-specific statistics and pattern-dependent statistics.

Methods and apparatus for soft data generation for memory devices

Methods and apparatus are provided for storing data in a multi-level cell flash memory device with cross-page sectors, multi-page coding and per-page coding. A single sector can be stored across a plurality of pages in the flash memory device. Per-page control is provided of the number of sectors in each page, as well the code and/or code rate used for encoding and decoding a given page, and the decoder or decoding algorithm used for decoding a given page. Multi-page and wordline level access schemes are also provided.

The present invention is all error detection and correction scheme that enables the use of Horner's algorithm for the computation of EDC syndromes from the computed error pattern. Specifically, 'transformed' EDC syndromes are computed during the read back of data and parity from the medium. The transformed syndromes are values of the polynomial whose coefficients occur in reverse order from that of the EDC codeword polynomial. In essence, by reversing the order of the coefficients, the Chien search processes the terms in descending order which is the right direction for Horner evaluation.

Computing an error detection code syndrome based on a correction pattern

Methods and apparatus are provided for a combined encoder/syndrome computer with a programmable parity level. In one embodiment, a circuit is disclosed that generates check symbols during an encoding operation and generates error syndromes during a decoding operation. The circuit comprises a plurality of subfilters grouped into a multiple degree polynomial filter, where the number of multiple degree subfilters is less than a maximum number of symbols of redundancy.

Method and apparatus for combined encoder/syndrome computer with programmable parity level

The present invention is an error detection and correction scheme that enables the use of Horner's algorithm for the computation of EDC syndromes from the computed error pattern. Specifically, 'transformed' EDC syndromes are computed during the read back of data and parity from the medium. The transformed syndromes are values of the polynomial whose coefficients occur in reverse order from that of the EDC codeword polynomial. In essence, by reversing the order of the coefficients, the Chien search processes the terms in descending order which is the right direction for Horner evaluation.

Method and apparatus for error detection

An error correction and miscorrection detection apparatus includes a memory buffer for storing user data contained in a data signal. A syndrome computer circuit generates a plurality of EDC syndromes form an EDC codeword. The EDC codeword includes user data encoded with a plurality of m-bit EDC parity symbols. The EDC codeword is encoded with plurality of n-bit ECC parity symbols to form the data signal, such that m>n. An ECC error correction circuit corrects the user data with an error signal generated for each corruption of the data signal. A completion is signal generated once correction of the EDC codeword is complete. A syndrome fix-up circuit is configured to adjust the EDC syndromes based on the received error signals. Once the completion signal is received, a miscorrection by the ECC error correction circuit is detected if a value of the adjusted syndromes is not equal to zero.

Herein is disclosed a method and apparatus for controlling power consumption of a disc drive in a portable computer based upon statistical characteristics of recent user disc access. This is accomplished by a disc drive that initially instantiates a set of thresholds, each of which govern transition into a corresponding power consumption mode. Next, the disc drive measures, at intervals, the time span since the disc drive was last issued a command. Prior to receipt of a new command by the disc drive, the disc drive is progressively transitioned into lower power consumption modes as the measured time span since the last command was issued meets each successive threshold. Following receipt of a new command by the disc drive, the threshold governing transition in to the next lower power consumption mode is adjusted based upon the measured time span.

Intelligent power management of disc drives

Embodiments of the present invention illustrate various configurations of a channel-to-controller interface. In one embodiment, width of symbols crossing the interface is fixed, as is the clock rate. In other embodiments, the symbol width is variable, and the clock rate is also varied based upon the size of the interface symbol width and the operation of the channel.

Configuration of channel-to-controller interface in a disc drive

The present invention pertains to a method for determining if data read from a storage medium has been read from physical block address (PBA) other than the expected PBA. Data that is stored on the data storage medium is encoded in accordance with a protocol that includes randomizing the data and combining the first k.times.2t bytes of the data with a PBA string, where t is the error correction capacity associated with the error correction technique used in the data storage system and k is the number of bytes of the PBA that are used in the PBA string. In addition, the data is k-way interleaved with parity data appended to it. When the data is read from the data storage medium, the data is decoded using a scheme corresponding to the encoding protocol. If errors are present in the data and exceed the error correction capacity, the first 2t bytes of each interleave are marked as erasures and a second correction is performed by an error correction unit. If the error values in each interleave are all the same, a PBA error is presumed to be the source of the errors. The actual PBA from which the data was read is then determined.

PBA recovery apparatus and method for interleaved reed-solomon codes

The present invention pertains to an apparatus and method for determining at most four error locations of RS encoded data read from a storage medium. The error location polynomial solver includes a controller, a multiplexer, storage registers, a data flow control unit, and various GF(256) arithmetic units. The GF(256) arithmetic units include GF(256) multiply unit, a GF(256) logarithmic ROM, a GF(256) anti-logarithmic ROM, a GF(256) square root unit, a GF(256) quadratic root finder, and a specialized integer division unit. The controller directs the operation of each of these components to perform one or more equation solver procedures that determine the appropriate number of roots. In an embodiment of the present invention, the controller is implemented as a state machine. The controller receives four coefficients representing an error location polynomial. The degree of the error location polynomial is determined in order for the controller to execute an appropriate equation solver procedure. The controller can execute one of four equation solver procedures based on the degree of the received error location polynomial.

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Soquel, CA, United States of America

Clifton James Williamson