Massachusetts Institute of Technology

Other

Clifton Fonstad, Jr

Markus Zahn

Edward Stuart Boyden

Anthony Zorzos

Jorg Scholvin

Jacob Bernstein

Joseph F Ahadian

Giovanni Talei Franzesi

Christian T Wentz

Brian Douglas Allen

Michael Baratta

Joseph John Rumpler

Joanna M London

Joseph John Rumpler, Ii

Described herein is a novel technique used to make novel thin III-V semiconductor cleaved facet edge emitting active optical devices, such as lasers and optical amplifiers. These fully processed laser platelets with both top side and bottom side electrical contacts can be thought of as freestanding optoelectronic building blocks that can be integrated as desired on diverse substrates for a number of applications, many of which are in the field of communications. The thinness of these platelets and the precision with which their dimensions are defined using the process described herein makes it conducive to assemble them in dielectric recesses on a substrate, such as silicon, as part of an end-fire coupled, coaxial alignment optoelectronic integration strategy. This technology has been used to integrate edge emitting lasers onto silicon substrates, a significant challenge in the field of silicon optoelectronics.

Highly integrable semiconductor device

In exemplary implementations of this invention, electrical connections are fabricated between two orthogonal surfaces by electroplating. The two surfaces are separated (except for the electrical connections) by a gap of not more than 100 micrometers. Multiple electrical connections may be fabricated across the gap. In preparatory steps, conductive pads on the two surfaces may be separately electroplated to build up 'bumps' that make it easier to bridge the remainder of the gap in a final plating step. Alternately, electroless deposition may be used instead of electroplating. In exemplary implementations, a 3D probe array may be assembled by inserting array structures into an orthogonal base plate. The array structures may be aligned and held in place, relative to the base plate, by mechanical means, including side hooks, stabilizers, bottom hooks, alignment parts and a back plate.

Methods and apparatus for three-dimensional microfabricated arrays

In exemplary implementations of this invention, high-throughput screening of a mammalian brain is performed to locate neural circuit targets of interest. A variety of search patterns may be used for this neural screening, including (a) iterative subdivision, (b) serial search, and (c) combinatorial. To perform this neural screening, an array of optical fibers (or an array of waveguides) is inserted into the brain. Alternately, the array is positioned adjacent to the brain. Each fiber or waveguide in the array is coupled to a light source (LED or laser). The brain has been previously sensitized to light, using genetically encoded optical neural control reagents, which are delivered either using viruses or via transgenic means. In the screening, the array is used to optically perturb the brain. For example, the neurons of the brain may be activated by one color of light, and/or silenced by another color of light.

Methods and apparatus for high-throughput neural screening

This invention may be implemented as a microstructure probe for delivering light of variable color and/or power, via a set of integrated lightguides, from an optical source (or set of sources) to regions spatially arranged 3-dimensionally, with a length scale of microns to millimeters. In exemplary embodiments of this invention, a microstructure probe comprises many lightguides and is adapted to be inserted into neural or other tissue. The lightguides run in parallel along at least a portion of the axis of the probe. The probe may deliver light to many points along the axis of insertion of the probe. This invention may be implemented as an array of two or more such probes (each of which comprises multiple lightguides). This array may be used to deliver light to neural tissue in a complex 3D pattern.

Methods and apparatus for microstructure lightguides

Highly integrable edge emitting active optical device and a process for manufacture of the same

A wafer having heterostructure therein is formed using a substrate with recesses formed within a dielectric layer. A magnetized magnetic layer or a polarized electret material is formed at the bottom of each recess. The magnetized magnetic layer or a polarized electret material provides a predetermined magnetic or electrical field pattern. A plurality of heterostructures is formed from on an epitaxial wafer wherein each heterostructure has formed thereon a non-magnetized magnetic layer that is attracted to the magnetized magnetic layer formed at the bottom of each recess or dielectric layer that is attracted to the polarized electret material formed at the bottom of each recess. The plurality of heterostructures is etched from the epitaxial wafer to form a plurality of heterostructure pills. The plurality of heterostructure pills is slurried over the surface of the dielectric layer so that individual heterostructure pills can fall into a recess and be retained therein due to the strong short-range magnetic or electrical attractive force between the magnetized magnetic layer in the recess and the non-magnetized magnetic layer on the heterostructure pill or between the polarized electret material in the recess and the dielectric on the heterostructure pill. Any excess heterostructure pills that are not retained in a recess formed within the dielectric layer are removed and an overcoat is applied to form a substantial planar surface.

Method and system for magnetically assisted statistical assembly of wafers

System for field assisted statistical assembly of wafers

Method and system for field assisted statistical assembly of wafers

In a method for bonding a silicon substrate to a III-V material substrate, a silicon substrate is contacted together with a III-V material substrate and the contacted substrates are annealed at a first temperature that is above ambient temperature, e.g., at a temperature of between about 150&deg; C. and about 350&deg; C. The silicon substrate is then thinned. This bonding process enables the fabrication of thick, strain-sensitive and defect-sensitive optoelectronic devices on the optimum substrate for such, namely, a thick III-V material substrate, while enabling the fabrication of silicon electronic devices in a thin silicon layer, resulting from the thinned Si substrate, that is sufficient for such fabrication but which has been thinned to eliminate thermally-induced stress in both the Si and III-V materials. The III-V material substrate thickness thereby provides the physical strength of the composite substrate structure, while the thinned silicon substrate minimizes stress in the composite structure.

Silicon on III-V semiconductor bonding for monolithic optoelectronic integration

Growing community of inventors

Arlington, MA, United States of America

Clifton Fonstad, Jr