International Business Machines Corporation

Clifford O Hayden

Susan B Stillman

Charles Franklin Webb

John Stephen Liptay

Steven T Comfort

Robert J Hurban

William Graham O'Keeffe

Donald W McCauley

John S Murdock, Jr

Daniel S Lowen

Pankaj Sabharwal

David R Snyder

A mechanism is provided in a data processing system for identifying and resolving issues in a distributed infrastructure. A log error processor monitors error logs of a plurality of data processing nodes within the distributed infrastructure. In response to the log error processor detecting an error in a given node within the distributed infrastructure, the log error processor provides error data for the error to the machine learning model and receiving from the machine learning model a set of potential solutions and associated confidence values. An operation extraction component extracts from each potential solution in the set of potential solutions a set of operations to resolve the error. A classifier component maps each set of operations to a set of executable operations that are executable by the given node. A solution scorer component determines whether to perform automatic resolution using a selected potential solution and its corresponding set of executable operations. In response to the solution scorer component determining to perform automatic resolution, an operation execution engine executes the corresponding set of executable operations on the given node.

Using cognitive technologies to identify and resolve issues in a distributed infrastructure

The invention provides a method for error detection of multi-threaded software. The method comprises executing an application which uses a logger that collects log statements, collecting at least one log statement from at least one application thread and storing the at least one log statement in memory, and allowing the collected log statement to be persisted in case of an error in a production environment.

System and method of error retention for threaded software

An instruction processing system and method which utilizes instruction completion to isolate errors, including those in the post-completion processing of operand stores, to an interval between checkpoints, while allowing the processing of checkpointing instructions to be overlapped with that of other instructions. Checkpoints are established before and after such instructions, and all processing (including that of operand stores) from before a checkpoint must be done prior to allowing instruction completion to move beyond the checkpoint. Nevertheless, instructions from beyond a checkpoint are allowed to be processed up to the point of completion while waiting for the checkpoint to be cleared. The point at which instructions must wait on a prior checkpoint is thus moved to the final phase of instruction processing (instruction completion), at significant performance advantage over a conventional implementation in which this waiting is done at instruction fetch, decode, or execution time.

Checkpoint synchronization with instruction overlap enabled

Method for processing checkpoint instructions to allow concurrent

A system and method for modifying program status words (PSW) with overlap enabled. According to the present invention, an instruction which modifies a PSW system mask, access key, or address space code is executed with overlap enabled. This instruction generates a new PSW. The new PSW is pushed into a queue. Once the instruction is complete, the new PSW becomes an architected PSW. If the instruction does not complete, then the new PSW is discarded. Once the new PSW is pushed into the queue, subsequent instructions may execute using the new PSW. Thus, instructions which modify the PSW system mask, access key, and address space code may execute with overlap enabled.

System and method for modifying program status word system mask, system

A Recovery Control Register is embodied as two multi-bit registers; a staged register and an immediate register. The immediate register contains the information which is read by the CP microcode and used during recovery. The staged register is a platform where a footprint can be assembled by the CP microcode before the retry checkpoint is changed. The CP microcode can operate on either register through the use of 'SET', 'AND' and 'OR' functions. The choice of these operators as well as the decision to separate the registers into bit ranges provides the microcode with maximum flexibility when setting up new checkpoint values. When a recovery algorithm requires that the recovery footprint change immediately, microcode operates on the immediate register. If, however, the recovery footprint needs to be synchronized with the event which requires the change, for example a store being released, the microcode puts the appropriate footprint into the staged register and issues a release signal to the completion/interrupt logic within the CP. When the release is processed and broadcast as a Completion Report a variable number of cycles later, the checkpoint is advanced and the immediate register is updated in the same cycle, thereby allowing for a crisp transition from one recovery window to the next.

Recovery control register

An improved error recovery system in which all operations which the Central Processor performs are categorized into one of a plurality of recovery types. The determination of category is made based on which architected and machine dependent facilities they manipulate and the manner in which the facilities are manipulated. This classification of instructions into types allows for the amount of checkpoint data to be minimized while allowing recovery to be generalized into broad algorithms instead of handling each operation independently. Furthermore, by applying this classification technique to various phases of execution (recovery windows) of instructions which modify system facilities before they complete, these instructions can also be retried with a minimum of hardware and algorithms.

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Jamaica Plain, MA, United States of America

Clifford O Hayden