Intel Corporation

Clifford L Ong

Eric A Karl

Zheng Guo

Tahir Ghani

Ian A Young

Mark T Bohr

Dmitri E Nikonov

Leonard P Guler

Rishabh Mehandru

Dinesh Somasekhar

Charles Henry Wallace

Mauro J Kobrinsky

Cory E Weber

Shem Ogadhoh

Sapumal Wijeratne

Mohammad Hasan

Sukru Yemenicioglu

Smita Shridharan

Yu-Lin Chao

Hans J Greub

Clifford J Engel

Eirc A Karl

Anandraj Devarajan

Gordon Carskadon

Xiaofei Wang

Embodiments of the present disclosure include integrated circuit structures having differentiated channel sizing, and methods of fabricating integrated circuit structures having differentiated channel sizing. In an example, a structure includes a memory region having a first vertical stack of horizontal nanowires having a first number of nanowires. The integrated circuit structure also includes a logic region having a second vertical stack of horizontal nanowires spaced apart from the first vertical stack of horizontal nanowires. The second vertical stack of horizontal nanowires has a second number of nanowires less than the first number of nanowires.

Integrated circuit structures having differentiated channel sizing

Integrated circuit (IC) static random-access memory (SRAM) bit-cell structures comprising pass-gate transistors having a different number of active channel regions than the number of active channel regions in pull-down transistors. A pass-gate transistor with fewer active channel regions than a pull-down transistor may reduce read instability of an SRAM bit-cell, and/or reduce overhead associated with read assist circuitry coupled to the bit-cell. In some examples, one or more pass-gate transistor channel regions are impurity doped or removed from either a top side or bottom side of the pass-gate transistors to depopulate the number of active channel regions relative to a pull-down transistor.

SRAM with channel count contrast for greater read stability

Embodiments described herein may be related to apparatuses, processes, systems, and techniques directed to electrical couplings between epitaxial structures and voltage sources within transistors in SRAM bit cells. Embodiments include direct electrical couplings between a backside contact metal (BM0) and a backside of an epitaxial structure to provide SRAM VCC voltage (SVCC) voltage, as well as electrical connection structures that electrically couple the BM0 to a front side of an epitaxial structure to provide SVCC voltage. Other embodiments may be described and/or claimed.

Backside electrical contact for PMOS epitaxial voltage supply

Uniform layouts for SRAM and register file bit cells are described. In an example, an integrated circuit structure includes a six transistor (6T) static random access memory (SRAM) bit cell on a substrate. The 6T SRAM bit cell includes first and second active regions parallel along a first direction of the substrate. First, second, third and fourth gate lines are over the first and second active regions, the first, second, third and fourth gate lines parallel along a second direction of the substrate, the second direction perpendicular to the first direction.

Uniform layouts for SRAM and register file bit cells

Disclosed herein are neural computing dies with stacked neural core regions as well as related methods and assemblies. In some embodiments, a neural computing die may include: a first neural core region; a second neural core region; and an inter-core interconnect region in a volume between the first neural core region and the second neural core region, wherein the inter-core interconnect region includes a conductive pathway between the first neural core region and the second neural core region, and the conductive pathway includes a conductive via.

Neural computing dies with stacked neural core regions

Systems and methods for precision writing of weight values to a memory capable of storing multiple levels in each cell are disclosed. Embodiments include logic to compare an electrical parameter read from a memory cell with a base reference and an interval reference, and stop writing once the electrical parameter is between the base reference and the base plus the interval reference. The interval may be determined using a greater number of levels than the number of stored levels, to prevent possible overlap of read values of the electrical parameter due to memory device variations.

Precise writing of multi-level weights to memory devices for compute-in-memory

Some embodiments include apparatuses having non-volatile memory cells, each of the non-volatile memory cells to store more than one bit of information; data lines, at most one of the data lines electrically coupled to each of the non-volatile memory cells; a circuit including transistors coupled to the data lines, the transistors including gates coupled to each other; and an encoder including input nodes and output nodes, the input nodes to receive input information from the data lines through the transistors, and the output nodes to provide output information having a value based on a value of the input information.

Multi-bit read-only memory device

An apparatus is provided which comprises: an interconnect comprising poly extending in a first direction; a power supply rail extending in a second direction, wherein the second direction is parallel to the first direction; and a memory array organized in rows and columns, wherein the rows are orthogonal to the columns, wherein the first and second directions are parallel to the rows of the memory array, wherein the memory array comprises bit-cells (e.g., 6T SRAM bit-cells) that are organized such that there are no gap bit-cells in the array.

Row based memory write assist and active sleep bias

Provided is a novel keeper circuit with a pull-up device whose strength changes for different operating supply levels so that the pull-up device is weaker for smaller supply levels and stringer for higher supply levels.

Growing community of inventors

Portland, OR, United States of America

Clifford L Ong