Cypress Semiconductor Corporation

Spansion Llc.

Infineon Technologies LLC

Micron Technology Incorporated

Other

Monterey Research, LLC

Clifford Alan Zitlaw

Stephan Rosner

Qamrul Hasan

Mark Alan McClain

Jeremy Mah

Yuichi Ise

Frank Edelhaeuser

Frankie F Roohparvar

Hagop A Nazarian

Hans Van Antwerpen

Anthony Le

Sergey Ostrikov

Sandeep Krishnegowda

Sylvain Dubois

Nobuaki Hata

Feng Quan Liu

Dawn M Hopper

Steven Walter Wilson

Yoav Yogev

Markus Unseld

Avi Avanindra

Shinsuke Okada

Ifat Nitzan Kalderon

Daisuke Nakata

Kfir Mizrachi

Wendy P Lee-Kadlec

Dubois Sylvain

Morgan Andrew Whately

A method can include, in a default mode of a memory device, decoding command data received on a unidirectional command address (CA) bus of a memory interface according to a first standard. In response to decoding a mode enter command, placing the memory device into an alternate management mode. In the alternate management mode, receiving alternate command data on the CA bus, and in response to receiving a command execute indication on the CA bus, decoding alternate command data according to a second standard to execute an alternate command. In response to decoding a mode exit command received on the CA bus according to the first standard, returning the memory device to the default mode. The memory interface comprises the CA bus and a data bus, and the CA bus and data bus comprise a plurality of parallel input connections. Corresponding devices and systems are also disclosed.

Methods, devices and systems for including alternate memory access operations over memory interface

A method can include: receiving a plurality of consecutive commands on a unidirectional command-address (CA) bus input of a discrete nonvolatile memory (NVM) device, the commands being synchronous with a timing clock; for each received command, determining if the command is an express read (NVR) command, if a command is determined to be an NVR command, determining if a next consecutive command is an NVR command, wherein consecutive NVR commands form an NVR command sequence; in response to the no more than the NVR command sequence, accessing read data stored in NVM cells of the NVM device; and driving the read data on parallel data input/outputs (I/Os) of the NVM device in a burst of data values, the data values of the burst being output in synchronism with rising and falling edges of the timing clock; wherein the CA bus input includes a plurality of parallel CA signal inputs. Related memory devices and systems are also disclosed.

Methods, devices and systems for high speed transactions with nonvolatile memory on a double data rate memory bus

In an embodiment, a method includes: receiving, via control lines of a parallel interface of a memory device, a first command and a first read command including one or more bits indicative of a first selection that causes a selector circuit to select data from a data memory portion of the memory device; providing, via data lines of the parallel interface, first data from the data memory portion using the selector circuit, where the provided first data is associated with the first read command; receiving, via the control lines, a second command and a second read command including one or more bits indicative of a second selection that causes the selector circuit to select data from an ECC memory portion; and providing, via the data lines, first ECC values from the ECC memory portion using the selector circuit, where the first ECC values are associated with the first data.

Circuit and method for reading ECC from memory

An apparatus includes a non-volatile memory (NVM) device coupled to a host, the NVM device including a processing device to: receive a communication packet from a server via the host computing system that is coupled to the NVM device and communicatively coupled to the server, the communication packet comprising clear text data that requests to initiate secure communications; perform a secure handshake with the server, via communication through the host computing system, using a secure protocol that generates a session key; receive data, via the host computing system, from the server within a secure protocol packet, wherein the data is inaccessible to the host computing system; authenticate the data using secure protocol metadata of the secure protocol packet; optionally decrypt, using the session key, the data to generate plaintext data; and store the plaintext data in NVM storage elements of the NVM device.

Secured communication from within non-volatile memory device

A method can include, in an integrated circuit device: at a unidirectional command-address (CA) bus having no more than four parallel inputs, receiving a sequence of no less than three command value portions; latching each command value portion in synchronism with rising edges of a timing clock; determining an input command from the sequence of no less than three command value portions; executing the input command in the integrated circuit device; and on a bi-directional data bus having no more than six data input/outputs (IOs), outputting and inputting sequences of data values in synchronism with rising and falling edges of the timing clock. Corresponding devices and systems are also disclosed.

Memory devices with low pin count interfaces, and corresponding methods and systems

A method can include storing first instruction data in a first region of a nonvolatile memory device; mapping addresses of the first region to predetermined memory address spaces of a processor device; executing the first instruction data from the first region with the processor device; receiving second instruction data for the processor device. While the first instruction data remains available to the processor device, the second instruction data can be written into a second region of the nonvolatile memory device. By operation of the processor device, addresses of the second region can be remapped to the predetermined memory address spaces of the processor device; and executing the second instruction data from the second region with the processor device.

Memory devices, systems, and methods for updating firmware with single memory device

A method can include, by operation of a host device, initiating a first transaction with at least a first device on a serial bus in synchronism with a clock, the first transaction having a predetermined response latency. The host device can initiate a second transaction on the serial bus in synchronism with the clock signal during the response latency. The first transaction and second transaction can be completed on the serial bus in synchronism with the clock. The serial bus is configured to transmit instruction data identifying transactions, target data identifying a destination for transactions, and data for transactions. Corresponding devices and systems are also disclosed.

Methods, devices and systems for high speed serial bus transactions

A device can include a plurality of regions, each region including a plurality of nonvolatile memory cells; a permission store configured to store a set of permission values, including at least one permission value for each region in a nonvolatile fashion; and access control circuits configured to control access to each region according to the permission value for the region, including one or more of requiring authentication to access the region, encrypting data read from the region, and decrypting data for storage in the region. Related methods and systems are also disclosed.

Nonvolatile memory device with regions having separately programmable secure access features and related methods and systems

Disclosed are apparatus and methods for programming a plurality of nonvolatile memory (NVM) devices. Each NVM device self-generates and stores a unique encryption key. Each NVM device concurrently receives an image from a multiple-device programming system to which all the NVM devices are communicatively coupled. Each NVM device encrypts the received image using such NVM device's unique encryption key to produce a unique encrypted image for each NVM device. Each NVM device stores its unique encrypted image within a nonvolatile memory of such NVM device. The unique encryption key can then be securely transferred to a host device for decrypting the image accessed from one of the NVM devices.

Encrypted gang programming

Example apparatus, systems, and methods receive a request for data associated with an address and responsively access a memory array to obtain the data. Embodiments transition a bus from a first state to a second state and after the transitioning of the bus, drive the data onto the bus.

Variable read latency on a serial memory bus

A peripheral device includes a function block to provide data in response to a request from a host device, a data channel coupled with the function block to transmit the data from the function block to a host device as one or more packets, and output logic coupled with the data channel and configured to indicate validity of the data transmitted via the data channel by causing a signal to transition for each of the one or more packets of the data transmitted to the host device via the data channel, and transmit the signal to the host device.

Method for providing read data flow control or error reporting using a read data strobe

Systems and methods embed a random-access non-volatile memory array in a managed-NAND system to execute the boot code or other time-sensitive applications. By embedding this random-access non-volatile memory in the managed-NAND system, either on the memory controller chip or as a separate chip within the managed-NAND system package, an application may be read with fast initial access time, alleviating the slow access time limitations of NAND Flash technology. Depending on the size of the application, the system may be configured to read the whole application content or only a time-critical portion from this embedded random-access non-volatile memory array.

Managed-NAND with embedded random-access non-volatile memory

Systems and/or methods are provided that facilitate employing a variable read latency on a serial memory bus. In an aspect, a memory can utilize an undefined amount of time to obtain data from a memory array and prepare the data for transfer on the serial memory bus. The serial memory bus can be driven to a defined state. When data is ready for transfer, the memory can assert a start bit on the serial memory bus to notify a host prior to initiating the data transfer.

Disclosed herein are system, apparatus, methods and/or combinations and sub-combinations thereof, for using a read data strobe signal received at a host device from a peripheral device to convey variable latency (flow) control or report an error in the data content read from the peripheral device. Reception of the read data strobe signal before a predetermined maximum latency time, provides variable latency control back to the host by indicating when valid data is available for capture. If the read data strobe signal is not received before expiration of a predetermined maximum latency time, the peripheral controller is indicating a read data error back to the host.

Data associated with a logical block address (LBA) may be received from a host system to be stored in the memory array. The LBA may be translated to a physical block address (PBA) by determining a first portion of the PBA and a second portion of the PBA. The data from the host system may be stored in the buffer space after determining the first portion of the PBA and before determining the second portion of the PBA. The data from the buffer space may be flushed to the memory array after determining the second portion of the PBA.

Growing community of inventors

Chico, CA, United States of America

Clifford Alan Zitlaw