Samsung Electronics Co., Ltd.

Cliff Reader

Le Trong Nguyen

Heonchul Park

Amjad Z Qureshi

Yoon Yung Lee

Jae Cheol Son

Tim Lu

Mark Frederiksen

A computer system includes three processors capable to operate concurrently&mdash;a scalar processor, a vector processor, and a bitstream processor. In encoding or decoding of video data, the vector processor performs operations that can be efficiently performed by a single instruction multiple data processor, for example, a discrete cosine transform (DCT) and motion compensation. The bitstream processor performs Huffman and RLC encoding or decoding. The bitstream processor can switch contexts to enable the computer system to process several data streams concurrently. The scalar and vector processors can be programmed to execute a single arithmetic or Boolean instruction. The bitstream processor cannot be programmed to execute a single arithmetic or Boolean instruction, but can be programmed to perform an entire video data processing operation. The computer system can handle different video standards. Different Huffman encoding and decoding tables are coded to share memory. Logic is supplied to derive correct Huffman codes from the coded tables stored in the shared memory.

Methods and apparatus for processing video data

An extension to existent vector instruction sets is presented in a form of new vector instructions which perform operations specialized for efficient digital video compression and decompression. A processor is designed to implement the arithmetic operation of each of these instructions in a single clock cycle, and some of the present instructions perform arithmetic operations selectively and directly on elements of the same registers.

Method for performing dead-zone quantization in a single processor

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Saratoga, CA, United States of America

Cliff Reader