Motorola Corporation

Cleon Petty

Ira E Baskett

Ray D Sundstrom

Dwight D Esgar

Wade H Nelson

Edward Derzawiec

A split level differential bus having first and second signals at first and second lines, respectively, for transmitting data from a typical driver to a typical receiver, includes a first independent voltage source for terminating the first line and a second independent voltage source for terminating the second line, the second independent voltage source providing a voltage level that is different from the voltage level provided by the first independent voltage source. A current switch circuit controlled by the driver for switching current from the first line to the second line. A level shifting circuit coupled between the first line and the receiver for level shifting the first signal by a predetermined voltage.

Split level bus

An single power supply ECL to TTL/CMOS translator is provided for converting a signal from differential ECL logic levels to TTL or CMOS compatible logic levels without introducing current spikes in the output signal during logic transitions. The differential ECL input signal is transformed into first and second differentially related signals having predetermined differential and single ended magnitudes. The first and second differentially related signals are then buffered and applied, as independent single ended signals, to first and second conduction paths controlling the first and second switching circuits in an output stage, respectively. The relative magnitudes of the first and second differentially related signals at the output of the buffer induce unequal slew rates at the input of the first and second conduction paths such that the first switching circuit is turned off before the second switching circuit is turn on thereby preventing simultaneous conduction and the associated undesirable current spikes flowing therethrough.

ECL to TTL/CMOS translator using a single power supply

An Emitter-Coupled-Logic (ECL) bus driver circuit provides differential ECL output signals designed for bus driving applications in response to receiving differential logic input signals and when disabled by a disabling signal places the differential outputs in a low state wherein a high impedance is presented thereat. The circuit includes a single logic gate and enable/disable gate that places the logic circuit in the ECL tri-level state using incremental current in conjuction with the current drain of the logic gate to reduce current drain otherwise required. In addition, time delay through the bus driver circuit is maintained at a minimum since only one gate is required to provide the differential function.

Differential emitter-coupled-logic bus driver

A three state gate having an output capable of assuming an active high, an active low, or a high impedance state is disclosed that has circuitry for removing the inherent Miller capacitive charge from an output transistor during the high impedance state. An output means includes an upper transistor for supplying current to the output and a lower transistor for sinking current from the output. A phase-splitter means coupled to the output means determines the conductivity of the upper and lower transistors. The phase-splitter means is responsive to an input signal and an output enable signal. A first transistor has a collector coupled to the base of the upper output transistor. A second transistor has a collector coupled to the base of the lower output transistor, and a base coupled to the emitter of the first transistor. A third transistor has a collector coupled to the base of the first transistor. A fourth transistor has an emitter coupled to an emitter of the third transistor and the output enable terminal. A fifth transistor has a base coupled to a collector of the fourth transistor, a collector coupled to a base of the phase-splitter transistor, and an emitter coupled to the base of the lower output transistor.

Tri-state logic gate having reduced Miller capacitance

A TTL flip-flop having improved AC and DC characteristics is provided including a higher resistance to output degradation and quicker transition time from a high state to a low state. The flip-flop includes a master section adapted to receive a data input signal and a clock pulse and includes a first output terminal for providing a Q output signal and a second output terminal for providing a Q output signal. A slave section is coupled between the master section and output buffers for latching the Q and Q outputs. The slave section comprises first and second latch portions, each responsive to a signal from the master section and coupled to one of the output buffers. The latch portions are similar and include a first transistor having a collector coupled to one output terminal and an emitter coupled to the master section. A second transistor has a first emitter coupled to the emitter of the first transistor and a third transistor has a collector coupled to the collector of the first transistor. A fourth transistor has a collector coupled to a second emitter of the second transistor and a base coupled to an emitter of the third transistor.

Master-slave flip-flop arrangement with slave section having a faster

In order to reduce the time it takes on-chip circuitry to generate an internal enabling signal from an external clock signal and an external enabling signal, the external clock signal is applied directly to the non-inverting input of an AB gate. The output of the AB gate and an external enabling signal are provided to first and second inputs of a NOR gate the output of which represents the internal enabling signal which is fed back to the inverting input of the AB gate. Thus, the clock signal propagates through only two stages of delay rather than three as is the case with prior art enabling circuitry.

Growing community of inventors

Tempe, AZ, United States of America

Cleon Petty