Rambus Inc.

Clemenz L Portmann

Kevin S Donnelly

Bruno Werner Garlepp

Pak Shing Chau

Donald C Stark

Stefanos Sidiropoulos

Ely K Tsern

Richard Maurice Barth

Paul G Davis

Jared L Zerbe

Grace Tsang

Thomas H Lee

John Bradly Dillon

Mark A Horowitz

Benedict C Lau

Wayne S Richardson

Mark G Johnson

Jun Y Kim

Roxanne T Vu

Leung Yu

Chaofeng Huang

Yiu-Fai Chan

Andy Chan

A method and apparatus for adjusting the performance of a memory system is provided. A memory system comprises a master device and a slave device. A memory channel couples the master device to the slave device such that the slave device receives the system operating information from the master device via the memory channel. The slave device further includes tuning circuitry within the slave device such that the performance of the memory system is improved.

Method and apparatus for adjusting the performance of a synchronous memory system

A method and apparatus for adjusting the performance of a memory system is provided. A memory system comprises a master device and a slave device. A memory channel couples the master device to the slave device such that the slave device receives the system operating information from the master device via the memory channel. The slave device further includes means for tuning circuitry within the slave device such that the performance of the memory system is improved.

A method and apparatus for adjusting the performance of a memory system is provided. A memory control device comprises a master device including a frequency detector, a memory channel, and a memory device coupled to the master device via the memory channel. The memory device includes a decoder designed to receive a control signal from the master device. A clock recovery and alignment circuit receives the control signal from the decoder and adjusts the operating frequency of the memory device in response to the control signal.

A synchronization circuit for gradually shifting the phase domain of a control signal to permit synchronization of a signal with a clock signal in a different phase domain in a system with a single frequency, but arbitrary phase relationship. The present invention allows a control signal in the phase domain of an internal clock to be synchronized with an external clock, when the phase domain of the external clock differs substantially from that of the internal clock. In synchronizing the control signal to the external clock, the present invention avoids the generation of runt pulses while providing a control signal synchronized to the external clock in the least amount of time feasible (i.e., with the lowest latency time). Because the present invention has no failure modes due to timing relationships, MTBF is infinite for failures caused by such relationships and therefore need not be a concern. This also implies that no risk is posed to the proper operation of the circuits driven thereby.

Apparatus and method for synchronizing a control signal

A synchronous dynamic random access memory device having an array of dynamic memory cells. The memory device includes input receiver circuitry to sample a value that is representative of a range of temperatures. In addition, the memory device includes a programmable register, coupled to the input receiver circuitry, to store the value that is representative of the range of temperatures.

Synchronous memory device having a temperature register

A low pass filter having a first mode of operation and a second mode of operation. The low pass filter includes a charging circuit, a capacitor circuit, and low power circuitry coupled to the capacitor circuit and the charging circuit. The capacitor circuit stores a first differential voltage when the low pass filter is operating in the first mode of operation. The capacitor circuit stores a second differential voltage when the low pass filter is operating in the second mode of operation. The second differential voltage is substantially equal to the first differential voltage. The charging circuit may include a charging current source coupled to a current steering circuit. The low pass filter may further include a load circuit coupled to the current steering circuit and the low power circuitry. The low pass filter may be used in a delay locked loop circuit or a phase locked loop circuit.

Low pass filter for a delay locked loop circuit

A phase interpolater circuit includes a first adjustable current supply to generate a first current that is based on the amplitude of a first controlled voltage and a first current mirror circuit to generate a second current that is based on the first current. The phase interpolater circuit further includes a first current steering switch to steer the second current to one of first and second nodes to generate a first voltage transition at one of the first and second nodes, the second current being steered to the first node when a first input signal is in a first state and to the second node when the first input signal is in a second state.

Method and apparatus for phase interpolation

Method and apparatus for synchronizing a control signal

A duty cycle correcting amplifier includes a first differential transistor pair with a pair of input nodes for receiving a differential input signal to be amplified. The first differential transistor pair has a first common node and a first pair of output nodes carrying differential output signals. A first current source is connected between the first common node and a first supply voltage. A second differential transistor pair has a pair of input nodes for receiving differential error input signals. The second differential transistor pair has a second common node and a second pair of output nodes coupled to the first pair of output nodes. The second differential transistor pair alters the common mode levels of each of the first pair of output nodes based on the differential error input signals to affect the duty cycle of the differential output signals. A second current source is connected between the second common node and the first supply voltage. A load circuit is connected between the first pair of output nodes and a second supply voltage. The load circuit provides a high impedance load between each node of the first pair of output nodes and a low impedance between each node of the first pair of output nodes and the second supply voltage. Capacitive circuitry is connected to each node of the first pair of output nodes. A converting amplifier has a pair of inputs for receiving the differential output signals. The converting amplifier amplifies and converts the differential output signals to a single ended signal constituting the output of the duty cycle correcting amplifier.

Conversion circuit with duty cycle correction for small swing signals, and associated method

A method and apparatus for an adjustable phase interpolator is provided. The adjustable phase interpolator includes a phase interpolator circuit that has a voltage input and a voltage output. The adjustable phase interpolator further includes a controllable capacitive load coupled to either the input or the output of the phase interpolator circuit. The controllable capacitive load is designed to add or subtract capacitance to the adjustable phase interpolator.

Variable delay element

A phase interpolator with noise immunity. The phase interpolator includes a voltage-to-current conversion circuit that receives a differential voltage and generates a differential current. The differential current is mirrored and provided to a phase Max/Min detector circuit and current switches. The phase Max/Min detectors may generate signals for a phase selector circuit. The current switches provide the mirrored current to a phase comparator and a load circuit in response to input vectors and a quadrant select signal. The phase comparator generates output waveforms from the phase interpolator.

Phase interpolator with noise immunity

A pulse generating circuit that includes an unbalanced latch and a feedback circuit. The unbalanced latch is configured to generate a latch signal having a predetermined state in response to application of power to the circuit. The feedback circuit is coupled in a negative feedback arrangement with the unbalanced latch and generates a pulse signal for a predetermined period of time in response to the latch signal.

Zero power reset circuit for low voltage CMOS circuits

Circuitry for adjusting the phase of an incoming periodic signal, typically a clock signal, throughout the entire period of the periodic signal. Phase adjustment circuitry has high resolution and employs only the number of delay elements in a delay chain necessary to span at least the period of the incoming signal or at least half the period in the case of dual chains receiving complementary clocks. Phase adjustment circuitry includes a delay chain of having a plurality of taps, a boundary detector for indicating when a tap is at a phase boundary of the incoming periodic signal, and selection circuitry for selecting one of the taps from the delay chain based on the boundary detector output and the selection circuitry input such that the selected tap is the desired phase adjustment of the incoming periodic signal and that the delay of the incoming signal is adjustable across its phase boundaries. Phase interpolation between the taps of the delay chain is employed to increase the resolution of the adjustment to the periodic signal. Duty cycle correction of the input clock and the selected output clock is employed to improve accuracy.

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Cupertino, CA, United States of America

Clemenz L Portmann