International Business Machines Corporation

Clement Y Poiraud

Edward Stanely Suffern

Claude R Galand

Joaquin Picon

Gerald Lebizay

Hong Linh Truong

Jean-Marie L Munier

Victor Spagnol

Andre Pauporte

Philippe Pierre Louis

Michel Geneste

Francois Jacob

Spiros Joseph Teleoglou

Xavier Jacquart

Michel A Lechaczynski

Paul P Viallon

Guy G Duforestel

Daniel Sazbon-Natansohn

Eric S Georges

Jean-yves Leboudec

A method and system aggregate data on multiple physically separate lower-speed E1/J1 channels of a communications network to generate higher bandwidth. A high speed data stream is first divided into lower bandwidth channels and transmitted through the network. The data arrives with varying delays depending on the physical characteristics of the network. Low bandwidth channels are aggregated together into a high bandwidth channel by determining the different geographical delay parameters among the lower speed channels, adjusting the transmission delays by alignment circuitry, and then combining the lower speed signals into one high bandwidth channel for the user. The transmission delay adjustment consists in adding a pseudo-random noise pattern to each of the lower bandwidth channels, measuring the time difference among all the channels, and then adjusting the time differences in the received data stream so that the combination of the signals produces a coherent higher bandwidth data stream. Because of the enhanced delay compensation mechanism, there is virtually no distance limitation in the transmission of data and if one of the lower physical telecommunication lines becomes inoperative, bandwidth recovery is provided.

System and method for creating N-times bandwidth from N separate

A multipurpose data communication network node for interconnecting both ATM and Variable Length (VL) input/output trunks with all combinations of node input versus output trunk connections. The network node includes ATM/VL Receive Adapters and ATM/VL Transmit Adapters, interconnected via a Switching device (44) operating on ATM like packets (i.e. ATM cells) only. The receive adapter includes means (41, 43) for deriving switchable cells from VL traffic possibly including ATM packets and provided over an input VL trunk and means (45, 46) for deriving switchable cells from ATM packets provided on input ATM trunk. The transmit adapter, includes means (47, 48) for reconstructing VL traffic to be fed onto an output VL trunk, and means (49, 50) for reconstructing ATM traffic to be fed onto an output ATM trunk; both means (47, 48) and (49, 50) being fed with switchable cells irrespective of the traffic origin, being it from VL or ATM trunks.

Multipurpose packet switching node for a data communication network

An elastic buffer is provided between two busses working with independent clocking. The buffer is implemented by a piece of RAM memory (37) partitioned into sectors (41), each of which contains successive memory addresses. Each sector (41), can be alternatively written and read, so that at a given moment, a sector in write mode and a sector in read mode may coexist. Each sector is controlled by a mark flag (MF), a set flag corresponding to a fully written sector, and a reset flag corresponding to a sector that has been read onto the destination bus. The mark flag of each sector is set, respectively reset, upon the event of a move in pointer, respectively move out pointer, reaching the next adjacent sector. For a given elastic buffer size, the size of the sectors (41) and the number of mark flags are adaptable to the specifications of the data flow between the origin and destination busses.

Elastic configurable buffer for buffering asynchronous data

Processing system for interpreting and carrying out a set of logically related instructions stored into a software program, the execution of a given instruction by the processing system involving the decoding and the execution of a corresponding set of microcommands. The processing system stores a signature portion corresponding to the macrocommand portion of a given instruction which is to be interpreted and executed, and signature data in response to the actual decoding and execution process of the microcommands involved in the execution of the instruction. The processing system further compares the computed signature data with the signature portion in order to detect the occurrence of an error in the decoding and execution process of the given instruction. In one embodiment of the invention, the processing system is such that one instruction is interpreted and executed in one elementary machine cycle. In a second embodiment of the invention, the execution of a given instruction involves the succession of multiple elementary machine cycles.

Processing system having device for testing the correct execution of

A method for storing the control code of a processor in a read only memory ROM (5) and in a read/write memory RAM (7) comprising a code area and a patch area. It consists in virtually dividing the control code in blocks of n instructions, storing the first instruction of each block into the code area of the read/write memory, and storing the n-1 following instructions of each block in the read only memory ROM. When an error is detected in at least one block, the first instruction of said block normally stored in the read/write RAM, is replaced by a branch instruction containing a branch address value so as to point to the patch area where the corrected block is stored. This method is implemented using a specific addressing circuit.

Method for storing the control code of a processor allowing effective

A serdes device includes circuitry for loading or reading bit configurations into or out of strings of latches of variable length nk+r, where n is the number of bits in a byte, k is the number of whole bytes and r is the number of residual bits, with r being smaller than n. Under the control of a service processor (8), there is formed a ring comprised of the latches of the serializer/deserializer register (14), the latches of the string considered (3 or 4) and a selected number (n-r) of latches of an extension register (16). The bytes to be loaded are sequentially sent to register (14), starting with the byte that contains the residual bits, and n bits are shifted out after loading each successive byte, so that after k+1 shifts the desired configuration will be contained in the string. For reading the contents of a string (for example, string 3), n bits are shifted, register (14) is read out, then k shifts of n bits each are performed, with register (14) being read out after each shift.

Device for serializing/deserializing bit configurations of variable

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Cagnes,Mer, France

Clement Y Poiraud