Altera Corporation

Cadence Design Systems, Inc.

Mips Technologies, Inc.

Arm Finance Overseas Limited

Clement Tse

Soumya Banerjee

Todd Michael Bezenek

Gordon Raymond Chiu

Deshanand Pratap Singh

Joshua David Fender

Vinay Agarwala

Systems and methods for using logic design processing to create an integrated circuit (IC). A method for creating an IC with a client device that is configured to perform all of the steps of receiving technology options and operating system options for the IC, selecting one of the technology options and one of the operating system options, receiving a subset of processor cores matching the selected technology option and the selected operating system option, identifying a particular processor core from among the subset of processor cores, customizing the particular processor core by adjusting at least one of default values for a system clock, a memory configuration, or a cache value based on the selected technology option to create a customized processor core configuration, presenting the customized processor core configuration in a graphical format and, in response, confirming the customized processor core configuration as a desired core configuration to be built, and sending device instructions to build an IC based on the desired core configuration.

Systems and methods for creating an integrated circuit with a remote device

A memory controller circuit is disclosed. The memory controller circuit is coupled to an external memory device. The memory controller circuit selectively generates error-correction information for a user input. The selection is based on whether the user input is one of predefined inputs. In order to facilitate that, the memory controller circuit includes a command processor circuit and a memory circuit. The error-correction information is stored within the memory circuit located within the memory controller circuit. Selectively generating the error-free correction information may significantly reduce the amount of memory storage that is required within the memory controller circuit.

Methods and apparatus for storing error correction information on a memory controller circuit

Mechanisms for measuring, analyzing, and presenting performance data associated with a memory controller system are described. The mechanisms include a performance monitor that detects and analyzes performance including efficiency and latency of a memory controller system. In addition to determining performance, the systems identifies reasons for loss of memory controller system efficiency. Moreover, the reasons, the efficiency, and the latency are analyzed and presented in a manner easily understandable to a user.

Methods and systems for measuring and presenting performance data of a memory controller system

A system and methods that facilitate the design process and minimize the time and effort required to complete the design and fabrication of an integrated circuits (IC) are described. The system and method utilize a plurality of repositories, rules engines and design and verification tools to analyze the workload and automatically produce a hardened GDSII description or other representation of the device. The system and method securely maintains synthesizable RTL on a server in a data center while providing designers access to portions of the mechanism by way of a network portal.

System and method for managing the design and configuration of an integrated circuit semiconductor design

A system for forming composite video images from one or more foreground images and one or more background images. In one embodiment, s sum of a suppressed foreground image signal with weight &#x3b1;, with one or more selected foreground colors suppressed, and a background image signal with weight 1&#x2212;&#x3b1;' (0&#x2266;&#x3b1;&#x2032;&#x2266;1) is formed, where a and &#x3b1;&#x2032; may vary from pixel to pixel and with time. In another embodiment, a shadow from a selected foreground image is impressed on selected pixels of a background image. In another embodiment, foreground suppression and shadowing are combined, optionally by retrofitting, using an existing &#x3b1;-mixer or a newly constructed &#x3b1;-mixer. Provision of a chroma key map allows a foreground image shadow to be prescribed pixel by pixel, including a transition region in which the shadowed image slowly disappears.

Growing community of inventors

Fremont, CA, United States of America

Clement Tse