Imec

Clement Merckling

Matty Caymax

Geoffrey Pourtois

Guy Brammertz

A semiconductor device includes a semiconductor substrate having a top surface, and at least one coated fin protruding perpendicularly from the surface and having a height h and side walls. The at least one coated fin further includes a core of one or more layers selected from the group consisting of (a) III-V compound layers and (b) a Ge layer, and a coating overlaying the core. The coating includes one or more metal oxide layers, at least one of which is aluminium. The device also includes a recess surrounding the at least one coated fin and being defined between two coated fins when more than one fin is present. The recess is filled up with a dielectric material so as to cover the coating on the side walls of the at least one fin up to a certain height h', which is less than the height h. The present disclosure also relates to a method for producing the semiconductor device.

Passivated III-V or Ge fin-shaped field effect transistor

The disclosure relates to a method for manufacturing a III-V device and the III-V device obtained therefrom. The method comprises providing a semiconductor substrate including at least a recess area and forming a buffer layer overlying the semiconductor substrate in the recess area. The buffer layer includes a binary III-V compound formed at a first growth temperature by selective epitaxial growth from a group III precursor and a group V precursor in the presence of a carrier gas. The first growth temperature is equal or slightly higher than a cracking temperature of each of the group III precursor and of the group V precursor.

III-V device and method for manufacturing thereof

The present invention is related to a method for manufacturing a low defect interface between a dielectric material and an III-V compound. More specifically, the present invention relates to a method for manufacturing a passivated interface between a dielectric material and an III-V compound. The present invention is also directed to a device comprising a low defect interface between a dielectric material and an III-V compound that has improved performance.

Method for manufacturing a low defect interface between a dielectric and a III-V compound

Manufacturing an III-V engineered substrate involves providing a base substrate comprising an upper layer made of a first III-V compound with a &#x3c;110&#x3e; or a &#x3c;111&#x3e; crystal orientation, forming an intermediate layer comprising at least a buffer layer of a second III-V compound, wherein the intermediate layer is overlying and in contact with the upper layer of the base substrate. Then a pseudomorphic passivation layer made of a group IV semiconductor material is grown so as to be overlying and in contact with the intermediate layer. This can enable an unpinned interface. The substrate surface can be smoother, implying fewer problems from surface stress. It can be used in electronic devices such as metal-oxide-semiconductor field effect transistors (MOSFETs), high electron mobility transistors (HEMTs), tunneling field effect transistors (TFETs), and optoelectronic devices.

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Schaerbeek, Belgium

Clement Merckling