Imec Vzw

Universiteit Gent

Katholieke Universiteit Leuven, Ku Leuven R&d

Katholieke Universiteit Leuven

Clement Merckling

Boon Teik Chan

Matty Caymax

Nadine Collaert

Guillaume Boccardi

Niamh Waldron

Joris Van Campenhout

Zheng Tao

Geoffrey Pourtois

Maria Ioanna Pantouvaki

Ashwyn Srinivasan

Salim El Kazzi

Irina Kulkova

Guy Brammertz

A structure is provided and includes (i) a substrate having a surface, the surface comprising a ternary or quaternary oxide having a first lattice parameter, the first lattice parameter being a lattice parameter of the ternary or quaternary oxide as it is present at the surface; and (ii) a layer of a perovskite oxide on the ternary or quaternary oxide, the perovskite oxide having a second lattice parameter, the second lattice parameter being a native lattice parameter of the perovskite oxide, wherein the first lattice parameter is larger than the second lattice parameter. A method for forming a perovskite oxide with an a-axis orientation is also provided.

Perovskite oxides with a-axis orientation

The disclosed technology is directed to a method of forming a qubit device. In one aspect, the method comprises: forming a gate electrode embedded in an insulating layer formed on a substrate, wherein an upper surface of the substrate is formed from a group IV semiconductor material and the gate electrode extends along the substrate in a first horizontal direction; forming an aperture in the insulating layer, the aperture exposing a portion of the substrate; forming, in an epitaxial growth process, a semiconductor structure comprising a group III-V semiconductor substrate contact part and a group III-V semiconductor disc part, the substrate contact part having a bottom portion abutting the portion of the substrate and an upper portion protruding from the aperture above an upper surface of the insulating layer, the semiconductor disc part extending from the upper portion of the substrate contact part, horizontally along the upper surface of the insulating layer to overlap a portion of the gate electrode; forming a mask covering a portion of the disc part, the portion of the disc part extending across the portion of the gate electrode in a second horizontal direction; etching regions of the semiconductor structure exposed by the mask such that the masked portion of the disc part remains to form a channel structure extending across the portion of the gate electrode; and forming a superconductor source contact and a superconductor drain contact on the channel structure at opposite sides of the portion of the gate electrode.

Method for forming a qubit device

A device and method for manufacturing a Si-based high-mobility CMOS device is provided. The method includes the steps of: (i) providing a silicon substrate having a first insulation layer on top and a trench into the silicon; (ii) manufacturing a III-V semiconductor channel layer above the first insulation layer by depositing a first dummy layer of a sacrificial material, covering the first dummy layer with a first oxide layer, and replacing the first dummy layer with III-V semiconductor material by etching via holes in the first oxide layer followed by selective area growth; (iii) manufacturing a second insulation layer above the III-V semiconductor channel layer and uncovering the trench; (iv) manufacturing a germanium or silicon-germanium channel layer above the second insulation layer by depositing a second dummy layer of a sacrificial material, covering the second dummy layer with a second oxide layer, and replacing the second dummy layer with germanium or silicon-germanium by etching via holes in the second oxide layer followed by selective area growth.

Si-based high-mobility CMOS device with stacked channel layers and resulting devices

An electrically-operated semiconductor laser device and method for forming the laser device are provided. The laser device includes a fin structure to which a waveguide is optically coupled. The waveguide is optically coupled to passive waveguides at either end thereof. The fin structure includes an array of fin elements, each fin element comprising Group III-V materials.

Laser devices

A method for formation of a transition metal dichalcogenide (TMDC) material layer on a substrate arranged in a process chamber of a molecular beam epitaxy tool is provided. The method includes evaporating metal from a solid metal source, forming a chalcogen-including gas-plasma, and introducing the evaporated metal and the chalcogen-including gas-plasma into the process chamber thereby forming a TMDC material layer on the substrate.

Method for formation of a transition metal dichalcogenide (TMDC) material layer

Method for manufacturing a Si-based high-mobility CMOS device with stacked channel layers, and resulting devices

A method for forming a semiconductor device is disclosed. The method includes providing a semiconductor substrate. The method also includes epitaxially growing on the semiconductor substrate a first part of a III-V semiconductor nanostructure. The method further includes covering the first part of the III-V semiconductor nanostructure with a layer of a first material. Additionally, the method includes removing a top portion of the layer of the first material. Still further, the method includes epitaxially growing on the first part of the III-V semiconductor nanostructure a second part of the III-V semiconductor nanostructure. The method additionally includes covering the second part of the III-V semiconductor nanostructure with a layer of a second material. The second material is different from the first material. Even further, the method includes removing a top portion of the layer of the second material.

Self-aligned nanostructures for semiconductor devices

The disclosed technology generally relates to semiconductor devices and more particularly to a gate-all-around semiconductor device, and methods of fabricating the same. In one aspect, the method comprises providing on a semiconductor substrate between STI regions at least one suspended nanostructure anchored by a source region and a drain region. The suspended nanostructure is formed of a crystalline semiconductor material that is different from a crystalline semiconductor material of the semiconductor substrate. A gate stack surrounds the at least one suspended nanostructure.

Gate-all-around semiconductor device and method of fabricating the same

An example semiconductor structure comprises a first surface and at least one nanowire, the at least one nanowire being perpendicular to the first surface, wherein the first surface is defect-poor and is made of a doped III-V semiconductor material, wherein the at least one nanowire is defect-poor and made of an undoped III-V semiconductor material having a lattice mismatch with the material of the first surface of from about 0% to 1%.

Vertical nanowire semiconductor structures

A method for growing a III-V semiconductor structure on a SiGesubstrate, wherein n is from 0 to 1 is provided. The method includes the steps of: (a) bringing a SiGesubstrate to a high temperature; (b) exposing the area to a group V precursor in a carrier gas for from 5 to 30 min, thereby forming a doped region at said area; (c) bringing the SiGesubstrate to a low temperature; (d) exposing the doped region to a group III precursor in a carrier gas and to a group V precursor in a carrier gas until a nucleation layer of III-V material of from 5 to 15 nm is formed on the nucleation layer; (e) bringing the SiGesubstrate to an intermediate temperature; and (f) exposing the nucleation layer to a group III precursor in a carrier gas and to a group V precursor in a carrier gas.

Growing community of inventors

Evere, Belgium

Clement Merckling