Lattice Semiconductor Corporation

Clement Lee

Ju Shen

Satwant Singh

Cyrus Y Tsui

Douglas C Morse

Jason Cheng

Albert L Chan

Benny Ma

Albert Chen

Mario Zancan

Victoria A Griffiths

A programmable device with logic blocks is configured to cascade product terms from one logic block to another to increase the logical input width of the product terms. Each logic block may produce a plurality of product terms based upon the selection of inputs from a routing structure. Logic blocks configured to receive cascaded product terms includes a plurality of AND gates corresponding to the plurality of product terms.

Programmable logic device with enhanced wide input product term cascading

A media access control processor includes a receiver co-processor and a transmitter co-processor. Each co-processor includes its own micro-controller. Depending upon the desired communication protocol being implemented, a programmable logic device controls the loading of an appropriate set of micro-instructions into the micro-controller's memory.

Flexible media access control architecture

A programmable device and method with generic logic blocks. Each generic logic block is configurable to perform product term logic functions and memory functions, such as RAM, dual-port RAM, ROM, CAM, FIFO and switch.

Device and method with generic logic blocks

An input/output (I/O) circuit or cell associated with a pin of a programmable logic circuit allows the pin to be configured as for bidirectional input and output operations, without requiring a second one-bit register to be configured from the configurable logic elements of the programmable logic circuit. The I/O cell can be used in parallel-to-serial, serial-to-parallel and shift register operations.

Programmable input/output cell with bidirectional and shift register capabilities

A method and a structure provide in a programmable logic device wide multiplexers without increasing delay and the number of interconnections in an input routing resource over corresponding multiplexer with less number of input signals. In one embodiment, each of a number of 8-input multiplexers shares both common input signals and common selection signals with a neighboring multiplexer. Even wider multiplexers can be achieved by cascading the multiplexers in a conventional manner.

Structure and method for implementing wide multiplexers

A programmable logic device having an internal tristate bus is provided. The internal tristate bus may be driven by a plurality of driving elements. Such a tristate bus, and the circuitry for supporting it, can be implemented on less surface area than the multitude of unidirectional buses, and supporting circuitry, which would otherwise be required for the same plurality of driving elements. Accordingly, the amount of surface area that is required to move information within a programmable logic device is reduced. Furthermore, in one embodiment, a arbitration logic circuit is provided for each driving element. These arbitration logic circuits cooperate to prevent the different elements from simultaneously driving the internal tristate bus. Accordingly, the integrity of the information on such bus is maintained.

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Portland, OR, United States of America

Clement Lee