Taiwan Semiconductor Manufacturing Comp. Ltd.

International Business Machines Corporation

Infineon Technologies Ag

National Central University

Clement Hsingjen Wann

Chih-Hsin Ko

Cheng-Hsien Wu

Yi-Tang Lin

Sey-Ping Sun

Neng-Kuo Chen

Ling-Yen Yeh

Chi-Yuan Shih

Chun Hsiung Tsai

Yi-Jing Lee

Chih-Sheng Chang

Chi-Wen Liu

Yu-Lien Huang

Ding-Kang Shih

Sung-Li Wang

Liang-Gi Yao

Ming-Huan Tsai

Yu-Ming Lin

Chin-Hsiang Lin

Yasutoshi Okuno

Jeff J Xu

Chun-Hsiung Tsai

You-Ru Lin

Cyril Cabral, Jr

Tsung-Lin Lee

Kuo-Feng Yu

Sunfei Fang

Shahaji B More

Yen-Yu Chen

Chih Chieh Yeh

Shao-Ming Yu

Hsin-Chih Chen

Christian Lavoie

Ming-Feng Shieh

Chih-Hao Chang

Cheng-Yi Peng

Chun-Wei Chang

Chang-Yun Chang

Feng Yuan

Zhijiong Luo

Tung Ying Lee

I-Sheng Chen

Huilong Zhu

Haining S Yang

Ming-Hsi Yeh

Chao-Ching Cheng

Brian Joseph Greene

Chia-Cheng Chen

Rajarao Jammy

Ru-Shang Hsiao

Chen-Yi Lee

Tsu-Hsiu Perng

Chi-Feng Huang

Chewn-Pu Jou

John J Ellis-Monaghan

Li-Chun Tien

Anthony Yen

Huan-Neng Chen

Fu-Lung Hsueh

Shinn-Sheng Yu

Po-Hsiang Huang

Sheng-Hsiung Chen

Fong-yuan Chang

Chun-Chieh Lu

Shou-Zen Chang

James Spiros Nakos

Da-Wen Lin

Ching-Feng Fu

Chun-Yung Sung

Chia-Jung Hsu

Chien-Wen Chen

Hung-Ming Chen

Chun-Hsiang Fan

Shih-Ting Hung

I-Ming Chang

Chih-Chao Yang

Lawrence Alfred Clevenger

Ching-Yu Chang

Ghavam G Shahidi

Vijay Narayanan

Timothy Joseph Dalton

Andrew Herbert Simon

Evgeni Petrovich Gousev

Terry Allen Spooner

Vamsi Krishna Paruchuri

Chung-Cheng Wu

Yun-Yu Wang

Erdem Kaltalioglu

Kuang-Hsin Chen

Chandrashekhar Prakash Savant

Kaushik Arun Kumar

Douglas C La Tulipe, Jr

Jen-Inn Chyi

Jui-Chien Huang

Andrew Joseph Kelly

Ying Di Zhang

Kern Rim

Huan-Chieh Su

Tsz-Mei Kwok

Wei-Sheng Yun

A semiconductor device and a method of forming the same are provided. The semiconductor device includes a substrate, a deep trench capacitor (DTC) having a portion within the substrate, and an interconnect structure over the DTC and the substrate. The interconnect structure includes a seal ring structure in electrical contact with the substrate, a first conductive via in electrical contact with the DTC, and a first conductive line electrically coupling the seal ring structure to the first conductive via.

Interconnect layout for semiconductor device

A semiconductor structure includes a first metal-dielectric-metal layer, a first dielectric layer, a first conductive layer, a second conductive layer, and a second dielectric layer. The first metal-dielectric-metal layer includes a plurality of first fingers, a plurality of second fingers, and a first dielectric material. The first fingers are electrically connected to a first voltage. The second fingers are electrically connected to a second voltage different from the first voltage, and the first fingers and the second fingers are arranged in parallel and staggeredly. The first dielectric material is between the first fingers and the second fingers. The first dielectric layer is over the first metal-dielectric-metal layer. The first conductive layer is over the first dielectric layer. The second conductive layer is over the first conductive layer. The second dielectric layer is between the first conductive layer and the second conductive layer.

Semiconductor structure, electronic device, and method of manufacturing semiconductor structure

Present disclosure provides a method including: forming a semiconductor stack having at least one SiGe layer; forming a plurality of fins from the semiconductor stack by a first etching operation, each of the plurality of fins comprising a first portion and a second portion over the first portion, the first portion being separated from the second portion by a SiGe portion; forming a poly gate stripe orthogonally over the plurality of fins; forming a recess on each of the plurality of fins abutting the poly gate; recessing the SiGe portion by a second etching operation through the recess; forming a first spacer and a second spacer to surround the SiGe portion; and removing the SiGe portion.

Manufacturing method for semiconductor structure having a plurality of fins

In a method of manufacturing a semiconductor device, a gate dielectric layer is formed over a channel region made of a semiconductor material, a first barrier layer is formed on the gate dielectric layer, a second barrier layer is formed on the first barrier layer, a first work function adjustment layer is formed on the second barrier layer, the first work function adjustment layer and the second barrier layer are removed. After the first work function adjustment layer and the second barrier layer are removed, a second work function adjustment layer is formed over the gate dielectric layer, and a metal gate electrode layer is formed over the second work function adjustment layer.

Method of manufacturing semiconductor devices and semiconductor devices

The present disclosure relates to a semiconductor device including a substrate having a top surface and a gate stack. The gate stack includes a gate dielectric layer on the substrate and a gate electrode on the gate dielectric layer. The semiconductor device also includes a multi-spacer structure. The multi-spacer includes a first spacer formed on a sidewall of the gate stack, a second spacer, and a third spacer. The second spacer includes a first portion formed on a sidewall of the first spacer and a second portion formed on the top surface of the substrate. The second portion of the second spacer has a thickness in a first direction that gradually decreases. The third spacer is formed on the second portion of the second spacer and on the top surface of the substrate. The semiconductor device further includes a source/drain region formed in the substrate, and a portion of the third spacer abuts the source/drain region and the second portion of the second spacer.

Gate spacer structures and methods for forming the same

A method of manufacturing a semiconductor device includes: providing a substrate comprising a surface; forming fins on the substrate; depositing a dummy gate electrode over the fins; forming a gate spacer surrounding the dummy gate electrode; forming lightly-doped source/drain (LDD) regions in the substrate on two sides of the gate spacer; performing a first treatment at a first temperature to repair defects in at least one of the dummy gate electrode, the gate spacer and the LDD region; forming source/drain regions in the respective LDD regions; removing the dummy gate electrode to form a replacement gate; depositing an inter-layer dielectric (ILD) layer over the replacement gate and the source/drain regions; and subsequent to the forming of the replacement gate, performing a second treatment at a second temperature, lower than the first temperature, to repair defects of the semiconductor device.

Semiconductor device with reduced trap defect and method of forming the same

The embodiments of mechanisms for doping wells of finFET devices described in this disclosure utilize depositing doped films to dope well regions. The mechanisms enable maintaining low dopant concentration in the channel regions next to the doped well regions. As a result, transistor performance can be greatly improved. The mechanisms involve depositing doped films prior to forming isolation structures for transistors. The dopants in the doped films are used to dope the well regions near fins. The isolation structures are filled with a flowable dielectric material, which is converted to silicon oxide with the usage of microwave anneal. The microwave anneal enables conversion of the flowable dielectric material to silicon oxide without causing dopant diffusion. Additional well implants may be performed to form deep wells. Microwave anneal(s) may be used to anneal defects in the substrate and fins.

Mechanism for finFET well doping

A method of fabricating a semiconductor structure having multiple semiconductor device layers is provided. The method comprises providing a bulk substrate and growing a first channel material on the bulk substrate wherein the lattice constant of the first channel material is different from the lattice constant of the bulk substrate to introduce strain to the first channel material. The method further comprises fabricating a first semiconductor device layer on the bulk substrate with the strained first channel material, fabricating a buffer layer comprising dielectric material with a blanket top surface above the first semiconductor layer, bonding to the blanket top surface a bottom surface of a second substrate comprising a buried oxide with a second channel material above the buried oxide, and fabricating a second semiconductor device layer on the second substrate.

Systems and methods for a semiconductor structure having multiple semiconductor-device layers

A semiconductor device includes a substrate, an isolation structure, a semiconductor fin, a semiconductor layer, and a gate structure. The isolation structure is disposed over the substrate. The semiconductor fin extends from the substrate and in contact with the isolation structure. The semiconductor layer is disposed on and in contact with the isolation structure. The gate structure covers the semiconductor layer and spaced apart from the semiconductor fin.

Semiconductor device and manufacturing method thereof

In a method of manufacturing a semiconductor device, a fin structure is formed by patterning a semiconductor layer, and an annealing operation is performed on the fin structure. In the patterning of the semiconductor layer, a damaged area is formed on a sidewall of the fin structure, and the annealing operation eliminates the damaged area.

Method of manufacturing a semiconductor device

A semiconductor structure includes a substrate, a conductive feature over the substrate, a dielectric layer over the conductive feature and the substrate, and a structure disposed over and electrically connected to the conductive feature. The structure is partially surrounded by the dielectric layer and includes a first metal-containing layer and a second metal-contain layer surrounded by the first metal-containing layer. The first and the second metal-containing layers include different materials. A lower portion of the first metal-containing layer includes a transition metal or a transition metal nitride and an upper portion of the first metal-containing layer includes a transition metal fluoride or a transition metal chloride.

Method and structure for semiconductor interconnect

Methods of manufacturing a semiconductor structure are provided. One of the methods includes: receiving a substrate including a first conductive region of a first transistor and a second conductive region of a second transistor, wherein the first transistor and the second transistor have different conductive types; performing an amorphization on the first conductive region and the second conductive region; performing an implantation over the first conductive region of the first transistor; forming a contact material layer over the first conductive region and the second conductive region; performing a thermal anneal on the first conductive region and the second conductive region; and performing a laser anneal on the first conductive region and the second conductive region.

Method for manufacturing semiconductor structure

Present disclosure provides a semiconductor structure, including a semiconductor fin having a first portion and a second portion over the first portion, a first conductive region abutting a first lateral surface of the first portion and a first lateral surface of the second portion, a metal gate having a bottom portion and an upper portion, the bottom portion being between the first portion and the second portion of the semiconductor fin, and the upper portion being over the second portion of the semiconductor fin, and a first spacer between the bottom portion of the metal gate and the first conductive region. A method for manufacturing the semiconductor structure described herein is also provided.

Semiconductor structure having fin with all around gate

Growing community of inventors

Carmel, NY, United States of America

Clement Hsingjen Wann