Sun Microsystems, Inc.

Clayton L Yee

Stefan Rusu

Alan C Rogers

Deviprasad Malladi

Sandeep A Aji

A method and apparatus to distribute spare cells into a standard cell region of an integrated circuit is described. An initial layout of standard cells is first generated by a place and route tool. Afterwards, the initial layout is processed by a spare cell distribution mechanism that simultaneously processes a directive file. The spare cell distribution mechanism distributes, according to a predefined criteria, a preselected cluster of spare cells within the initial layout of standard cells. This processing results in an optimal distribution of spare standard cells within the standard cell region of the semiconductor. The spare cell distribution mechanism also inserts vertical wire terminators into the standard cell region to promote vertical routing, and thus shorter routing paths. In addition, the spare cell distribution mechanism inserts ground connectors and power connectors in the standard cell region to generate a ground and power paths. The outputs of the inserted spare cells may be connected to the ground and power paths until they are subsequently re-routed to correct logic defects in the standard cell region.

Method and apparatus to distribute spare cells within a standard cell

A package for an integrated circuit is described. The package houses an integrated circuit with a signal quality sensitive integrated circuit element, such as a voltage controlled oscillator of a phase-locked loop. A package-mounted storage capacitor is positioned on the package body to generate a precision control signal. A signal path is constructed between the package-mounted storage capacitor and the integrated circuit to route the precision control signal to the integrated circuit. The relatively short signal path from the package-mounted storage capacitor to the integrated circuit has reduced parasitic capacitance, inductance, and resistance to maintain the quality of the precision control signal. To improve signal quality, certain portions of the signal path are electrically isolated with a shielding trace.

Integrated circuit package with external storage capacitor for improved

A method and apparatus to model the power network of a VLSI circuit is described. The method includes the step of extracting the power network associated with a semiconductor circuit layout. A compacted power network is then derived from the power network. The compacted power network includes a compacted primary resistive network to characterize the electrical resistance of the power trunks within the semiconductor circuit layout. The compacted power network also includes a compacted secondary resistive network to characterize the electrical resistance of power straps that deliver power to transistors within the semiconductor circuit layout. The compacted power network constitutes a network of compaction component values that correspond to functional regions in the semiconductor circuit layout. Each of the compaction component values includes an associated set of spacial compaction values that characterize the total resistance of a functional region. The operation of the compacted power network is simulated on a circuit simulation program to identify areas in the compacted power network that do not comply with predetermined power network performance criteria, such as electromigration limits and voltage drop limits. The semiconductor circuit layout is then reconfigured to satisfy the predetermined power network performance criteria.

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San Francisco, CA, United States of America

Clayton L Yee