Silicon Laboratories Inc.

National Instruments Corporation

Clayton H Daigle

Xiaodong Wang

Axel Thomsen

Christopher G Regier

Jinwen Xiao

John M Khoury

Jeffrey Lee Sonntag

Alan Lee Westwick

Pavel Konecny

Dewitt Clinton Seward, Iv

Shahram Tadayon

Jeffery Tindle

Matt Williamson

Lauren Sjoboen

Antony Wangsanata

Abdulkerim Coban

Gregory A Hodgson

Yan Zhou

Alessandro Piovaccari

Mohamed M Elsayed

Attila Zolomy

Shouli Yan

Jeffrey A Tindle

Subrata Roy

Younas Abdul Salam

DeWitt C Seward

An electromagnetic pulse detector in an integrated circuit includes one or more peak hold circuits coupled to one or more traces in the integrated circuit and configured to asynchronously detect voltage spike(s) on the one or more traces and store voltage value(s) corresponding to the voltage spike(s). One or more comparator circuits are coupled to the peak hold circuits to compare the voltage values corresponding to the voltage spikes to one or more threshold voltage values. Storage locations are coupled to the comparator circuits to store indications of the voltage spike(s) being greater than the threshold voltage value to thereby indicate detection of an electromagnetic pulse.

Asynchronous peak hold circuit on an integrated circuit trace to monitor for voltage spikes caused by an electromagnetic pulse

An apparatus includes a power management circuit to receive an input voltage and to generate and provide a first output voltage to an energy storage device. The power management circuit further generates and provides a second output voltage to a load. The first output voltage is greater than the input voltage, and the second output voltage is smaller than the first output voltage. The apparatus further includes a monitor circuit to monitor the first output voltage and to provide a signal to the load to indicate when the load may perform an operation.

Apparatus for improving the effective performance of a power source and associated methods

A system and method for controlling the current to an LED array is disclosed. The system comprises a microcontroller and an external transistor. The microcontroller has access to the relevant voltages in the circuit, including the voltage across the sense resistor, the voltage at the drain of the external transistor and the high voltage input. By monitoring these voltages, the microcontroller may be able to control the gate input to the external transistor so as to control the current in the LED array. Further, the microcontroller includes provisions to allow for dimming of the LED array, if desired. This configuration allows for post-manufacturing changes to the operation of the system without any hardware modifications.

LED driver control using MCU

A system and method of allowing a network device to receive a customized version of a reference design is disclosed. In one embodiment, many values that may be subject to customization are no longer fixed by the reference design. Rather, the reference design utilizes rewritable non-volatile memory to store a set of customization values that can be changed, based on a customer's preference. The system also includes a configuration tool, which interfaces with the network device. Using vendor-unique commands, the configuration tool is able to initialize this set of customization values to the values requested by the customer. In operation, the reference design is downloaded into the network device. The configuration tool is then used to establish the customized parameters for a particular customer. This process allows the manufacturer to create one reference design, which can be customized without the need to modify the code or recompile the source code.

Over the air image configuration

A system and method of allowing a network device to enter RF test mode without changing the software image or attaching cables to it is disclosed. In one embodiment, the software image loaded into the network device has the capability to execute in both normal operating mode and RF test mode. A command is issued by a RF test tool which instructs the network device to enter one of one or more different RF modes. In certain embodiments, the network device remains in this RF test mode for a predetermined period of time. In other embodiments, the network device remains in this RF test mode until the power is cycled.

Over the air commands for RF testing

An integrated circuit (IC) includes a plurality of pads adapted to send or receive signals, and a plurality of mixed signal interface blocks, each of which is coupled to a corresponding pad in the plurality of pads. Furthermore, each mixed signal interface block in the plurality of mixed signal interface blocks is adapted to be configurable to provide selected functionality independently of the other mixed signal interface blocks.

Apparatus for mixed signal interface circuitry and associated methods

A successive approximation register (SAR) ADC includes an SAR comparator circuit including first and second inputs, a control input, and first and second outputs. The SAR comparator circuit further includes a plurality of capacitors coupled to the first and second inputs and includes a plurality of switches configured to couple the plurality of capacitors to one of a first voltage and a second voltage. The SAR ADC further includes a calibration circuit coupled to the first and second outputs and to the control input of the SAR comparator. The calibration circuit is configured to control the plurality of switches to selectively couple the plurality of capacitors to one of the first and second voltages to provide a calibration signal to the SAR comparator circuit. The calibration circuit is configured to calibrate the SAR comparator based on corresponding output signals at the first and second outputs.

Method and apparatus for calibration of successive approximation register analog-to-digital converters

An integrated circuit (IC) includes a plurality of pads adapted to communicate signals with a circuit external to the IC, and a first mixed signal interface block coupled to a first pad in the plurality of pads, where the first mixed signal interface block is adapted to receive a first trigger signal from the circuit external to the IC and to provide a second trigger signal. The IC further includes a second mixed signal interface block coupled to a second pad in the plurality of pads, where the second mixed signal interface block is adapted to receive and track a first input signal from the circuit external to the IC in a first mode of operation of the IC. The second mixed signal interface block is further adapted to generate, in response to the second trigger signal, a first output signal based on the first input signal and to provide the first output signal to a digital core of the IC in a second mode of operation of the IC, where the power consumption of the IC is lower in the first mode of operation than in the second mode of operation.

Apparatus for mixed signal interface acquisition circuitry and associated methods

A method of configuring an analog-to-digital converter (ADC) includes configuring the ADC to operate in one of a low-pass filter mode and a band-pass filter mode according to a value of a control signal. In at least one embodiment, the method further includes configuring an integrator gain of the ADC and a feed-forward gain of the ADC based on selection of one of a low-intermediate frequency (LIF) mode and a zero-intermediate frequency (ZIF) mode.

Multi-mode analog-to-digital converter

In an embodiment, the present invention includes a latch circuit having a first input to receive a data signal and a second input to receive a clock signal. This latch circuit may have a first pair of transistors including a first transistor gated by the data signal and a second transistor gated by an inverted data signal and a second pair of transistors including third and fourth transistors gated by the clock signal. The first transistor may be coupled to the third transistor at a first inter-latch node and the second transistor coupled to the fourth transistor at a second inter-latch node. A reset circuit may be coupled to the latch circuit to maintain the first and second inter-latch nodes at a predetermined voltage level when the clock signal is inactive.

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Pflugerville, TX, United States of America

Clayton H Daigle