United Microelectronics Corp.

United Semiconductor Corp.

Topic Semiconductor Corp.

Claymens Lee

Gary Y Hong

Jean-Ming Lee

The present invention provides a method for hardware reduction in the echo canceller and the near-end crosstalk canceller. The method applies an N (N is a positive integer) times divide frequency sampling operation onto the input data list of the echo canceller first (and the near-end crosstalk canceller). Then, it applies an N times multiply frequency sampling operation onto the output data list of the echo canceller (and the near-end crosstalk canceller) to generate a multiplied frequency data list. Afterwards, a low pass filter operation is applied to the multiplied frequency data list to generate a low pass data list to eliminate the echo signal (and the near-end crosstalk signal). The present invention reduces the number of the taps in the echo canceller and the near-end crosstalk canceller by using the digital signal process technique. Therefore, the area of the whole communication IC occupied by the echo canceller and the near-end crosstalk canceller can be reduced.

Method for hardware reduction in echo canceller and near-end crosstalk canceller

An apparatus of a digital echo canceller comprises a first-set delay circuits, a selector, a second-set delay circuits, a plurality of multipliers and an adder. The first-set delay circuits are arranged into groups, and each group has N delay circuits. An exhaustive search function is carried out to produce a plurality of energy sums. The selector will select the biggest energy sum to serve as a significant part and then transmit to the outputs of the second-set delay circuits, the multipliers and the adder. An estimated echo signal is produced to cancel the echo signal.

Apparatus of a digital echo canceller and method therefor

An apparatus of a digital echo canceller and method therefor, a designed selector is used values of receiving and input signals to estimate the length of a cable. The response values of an insignificant part of the echo signal can be selected. Multiplication and addition operations are carried out in a response region of a significant part of the echo signal. An estimated echo signal is produced to cancel the echo signal, unnecessary operations and the cost of a hardware can be reduced.

Apparatus for a digital echo canceller and method therefor

A method to reduce the inverse-narrow-line-effect is described in which an active region and an isolation region are defined on a substrate. A doped region is formed adjacent to the substrate surface, wherein the area of the doped region includes the isolation region and the edge of the active region. The depth of the doped region is shallower than that of the source/drain region formed subsequently. A shallow trench is formed thereafter in the isolation region adjacent to the active region, such that the doped region located in the substrate at the edge of the active region is retained. A liner oxide layer is further formed on the inner wall of the shallow trench. An oxide layer, which is as high as the surface of the cap layer, is formed to fill the trench. After the removal of the pad oxide layer and the cap layer, a gate oxide layer and a gate are formed on the substrate.

Method to reduce inverse-narrow-width effect

A method of manufacturing a shallow trench isolation in a substrate. The substrate has a pad oxide layer and a mask layer formed thereon in sequence and a trench penetrating through the mask layer and the pad oxide layer and into the substrate. A thermal oxidation process is performed to form a liner oxide layer on a portion of the substrate exposed by the trench. A spacer is formed on the sidewall of the mask layer, the pad oxide layer and the trench. An oxidation process is performed to oxidize a portion of the substrate under a portion of the liner oxide layer located on the bottom of the trench. An insulating layer is formed over the substrate and filling the trench. A planarization process is performed to remove a portion of the insulating layer until the mask layer is exposed. The mask layer and the pad oxide layer are removed.

Method for manufacturing shallow trench isolation

A method to lower the parasitic capacitance is described, in which a low dielectric constant air-gap is formed in the dielectric layers at both sides of the gate to lower the parasitic capacitance present between the gate and the source/drain region. The air-gap is formed by forming spacers at both sides of the gate, followed by forming a first dielectric layer with its height lower than the top of the spacers. Thereafter, the spacers are removed by wet etching to form a hole with its top narrower than its bottom. A second dielectric layer is further formed, by a deposition technique with a weaker step coverage capability, to encapsulate the hole and to cover the substrate, wherein the encapsulated hole is the air-gap.

Method to reduce parasitic capacitance

A method for fabricating an inter-metal dielectric layer. Several conducting wires are formed on a substrate, and openings lie between the adjacent conducting wires. A first dielectric layer fills the openings, and the surface of the first dielectric layer is lower than that of the conducting wires. A spacer is formed on a sidewall of each of the conducting wires. The first dielectric layer is removed to expose the bottom of the spacer. A second dielectric layer is formed to cover the conducting wires.

Method for fabricating inter-metal dielectric layer

A method of forming flash memory. The method includes forming buried bit lines before the production of shallow trench isolation (STI) structures. The steps for producing the STI structures include forming a pad oxide layer and a silicon nitride layer. A plurality of openings that expose the pad oxide layer is formed in the silicon nitride layer. These openings are located directly above the buried bit lines. Silicon dioxide is deposited to form a silicon dioxide layer that fills these openings. The silicon dioxide layer is capable of preventing the buried bit lines from being cut into segments in subsequent trench-isolation operations.

Method of forming a flash memory

A method of fabricating a silicide layer on a gate electrode is described. A gate oxide layer is formed on a substrate. A gate electrode is formed on a portion of the gate oxide layer. A spacer is formed on a sidewall of the gate electrode to cover the other portion of the gate oxide layer. The spacer is removed to expose a portion of the gate oxide layer. A metallic layer is formed over the substrate to cover the gate electrode and the gate oxide layer. An annealing step is performed to transform the metallic layer in contact with the gate electrode and the source/drain region into a silicide layer. The remaining metallic layer is removed.

Method of fabricating silicide layer on gate electrode

A method of fabricating a flash memory. After the formation of a trench isolation structure, openings are formed, in a direction perpendicular to the orientation of the trench isolation structure, in order to form a buried bit line. A spacer is formed on the opening sidewall of the bit line in which the distance between a top of the spacer and the interface of a substrate and a pad oxide layer is the depth of the source/drain region. The opening is then filled with a doped polysilicon conducting layer used as the buried bit line. The dopant from the polysilicon conducting layer is driven into the substrate to form the source/drain region.

Method of fabricating flash memory

A method for fabricating a metal-oxide semiconductor (MOS) transistor on a semiconductor substrate is described. The invention introduces an air chamber with a low dielectric constant between the gate and the source/drain region so as to lower the fringing electric field between the gate and the source/drain region. Moreover, the dielectric constant of the dielectric layer between the gate and the source/drain region is reduced. Therefore, the gate-to-drain capacitance is decreased in the MOS transistor.

Method for fabricating metal-oxide semiconductor transistor

A method of forming the gate terminal of a device. The method includes forming spacers on top of the gate polysilicon layer and near the side edges thereof, and then etching the gate polysilicon layer to form a groove using the spacers as a mask. Hence, the exposed surface area of the gate polysilicon layer is increased. Finally, a metal silicide layer is formed over the gate polysilicon layer, producing a low resistance gate.

Method for forming gate terminal

A method for forming a shallow trench isolation structure. A pad oxide layer is formed over a substrate. A hard mask layer is formed over the pad oxide layer. A portion of the hard mask layer, the pad oxide layer and the substrate is removed to form a trench in the substrate. Insulation material is deposited into the trench to form an insulation plug. The hard mask layer is removed to expose the sidewalls of the insulation plug. Spacers are formed on the exposed sidewalls of the insulation plug. Ions are implanted into the substrate. The pad oxide layer, the spacers and a portion of the insulation plug are removed. Finally, a gate oxide layer thicker in region around the edge of the insulation plug is formed over the substrate by oxidation.

Method for forming shallow trench isolation structure

A method for manufacturing a flash memory with a shallow trench isolation and a buried bit line. In the invention, the shallow trench isolation is used as an isolation region, so that the size of the devices can be greatly reduced and the integration of the devices can be greatly increased. Additionally, the shallow trench isolation is formed in the substrate before the buried bit line implantation step is performed, so that the short channel effect caused by the lateral diffusion of the doped ions can be eliminated. Moreover, since the neighboring doped regions are electrically coupled to each other through the polysilicon layer, the access rate of the flash memory can be enhanced.

Method of manufacturing flash memory

A method for manufacturing a comb-shaped lower electrode for a DRAM capacitor including the steps of providing a substrate having a transistor and an insulating layer formed thereon, wherein the insulating layer contains a contact window opening exposing a source/drain region of the transistor; then, forming a polysilicon layer over the insulating layer, the contact window opening and the exposed source/drain region; next, forming a hemispherical grain silicon over the polysilicon layer. Thereafter, an oxide layer is formed over the hemispherical grain silicon, and then a silicon nitride layer is formed over the gaps between the hemispherical grain silicon exposing portions of the oxide layer. In the subsequent step, a plurality of hard mask layers are formed over the oxide layer not covered by the silicon nitride layer, and finally the silicon nitride layer, the oxide layer and portions of the polysilicon layer are removed using the hard mask layers to form a plurality of trenches.

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Kaohsiung Hsien, Taiwan

Claymens Lee