Lsi Corporation

Lsi Logic Corporation

Claus Pribbernow

Stephan Habel

Stefan G Block

Herbert Johannes Preuthen

Stefan G Auracher

Andreas Hils

David Parker

Juergen Dirks

Srinivasa Rao Kothamasu

Sakthivel Komarasamy Pullagoundapatti

Venkat Rao Vallapaneni

Farid Labib

Shrinivas Sureban

Manisha R Patel

James T Imper

A system and method for optimizing slave transaction ID width based on sparse connection between multiple masters and multiple slaves in a multilayer multilevel interconnect system-on-chip (SOC) architecture are disclosed. In one embodiment, slave transaction ID widths are computed for a first processing subsystem and a second processing subsystem including multiple masters and multiple slaves. Further, a slave transaction ID for each master to any slave in the first processing subsystem and in the second processing subsystem is generated based on the computed slave transaction ID width. Furthermore, sparse connection information between the multiple masters and multiple slaves is determined via a first bus matrix in the first processing subsystem. A first optimized slave transaction ID for each master to any slave in the first processing subsystem is then generated by removing don't care bits in each generated slave transaction ID based on the sparse connection information.

System and method for optimizing slave transaction ID width based on sparse connection in multilayer multilevel interconnect system-on-chip architecture

In one embodiment, a circuit has multiple flip-flops with gated clock inputs controlled by an enable signal, where the clock signal is gated in order to reduce power consumption by the circuit. The circuit has an error detection and correction (EDC) module that is active when the enable signal is low in order to detect and correct soft errors of the flip-flops. The EDC module generates and stores an error-correction code based on the data outputs of the flip-flops. The EDC module then compares the stored error-correction code to a presently generated error-correction code, where if they are not identical, then the EDC (a) determines (i) that a soft error has occurred and (ii) which flip-flop suffered the soft error and (b) flips a corresponding error-correction signal to provide a correct corresponding output signal while the enable signal is low.

Soft-error detection for electronic-circuit registers

An improvement to an integrated circuit of a type having a test enable line for enabling an electrical test of the integrated circuit only when the test enable line is at a logical high value, and output lines that are only used during the electrical test of the integrated circuit, where the improvement is a switch circuit for disabling a state change in the output lines when the test enable line is at a logical low value. In this manner, the output lines do not switch during functional use of the integrated circuit, and cannot be aggressors on the data signals that are carried by the data lines that are used during the functional use of the integrated circuit. In addition, these non-switching output lines can act as guard traces that run between the data lines, further electrically isolating the data lines from one another. Further, because they do not switch during functional use of the integrated circuit, the overall power consumption of the integrated circuit is reduced.

Test pin gating for dynamic optimization

A data-processing system and method are disclosed, which include a cached processor for processing data, and a plurality of memory components that communicate with the cached processor. The cached processor is separated from the memory components such that the cached processor provides support for the memory components, thereby providing a diffused memory architecture with diffused memory capabilities. The memory components can constitute, for example, memory devices such as diffused memory, matrix memory, R-Cell memory components, and the like, depending on design considerations.

All purpose processor implementation to support different types of cache memory architectures

A circuit which includes an IP cell having a function select input signal line, combinatorial logic having an output connected to the function select input signal line of the IP cell, a configuration register having an output connected to an input of the combinatorial logic, wherein a high/low input signal line is also connected to the combinatorial logic, wherein the circuit provided that the configuration register receives configuration data during a start-up sequence, and configuration data is held by the combinatorial logic as the configuration register powers down during a functional mode.

Config logic power saving method

An application specific configurable logic IP module includes (1) a system level configuration controller; (2) at least one standardized interconnect communicatively coupled to the system level configuration controller; (3) at least one standardized configuration port for programming the application specific configurable logic IP module; (4) an embedded programmable logic fabric, communicatively coupled to the system level configuration controller and the at least one standardized interconnect, for mapping arithmetic functions into standard cells; (5) at least one scalable configurable logic module; and (6) a programmable routing matrix. The system level configuration controller is suitable for selecting a standard for the at least one standardized interconnect, the at least one standardized configuration port, and a number of embedded programmable logic functions, and for controlling the programmable routing matrix.

Application specific configurable logic IP

A data-processing system and method include a processor core associated with a cache controller. A plurality of cached memory components is associated with the processor core and the cache controller. A cached processor is provided, which supports a plurality of varying sizes of instruction and data cache, wherein the cached processor comprises a processor core separated from the cache controller and the plurality of cached memory components, thereby permitted the cached processor to support varying sizes of cache memory in a flexible memory arrangement thereof.

Data-processing system and method for supporting varying sizes of cache memory

A method of placing a clock signal supply network in a design representation for an integrated circuit. The design representation may comprise a plurality of clockable circuit cells. The method may comprise identifying a first of the clockable circuit cells in the design representation. The method may further comprise identifying a second of the clockable circuit cells in the design representation. The second clockable circuit cell may have a clock timing dependent relation relative to the first clockable circuit cell. The method may further comprise configuring the clock signal supply network. The clock signal supply network may be configured to supply respective clock signals to the first and said second clockable circuit cells. The clock signal supply network may be configured to route the respective clock signals such that a timing difference between the respective clock signals is protected from process, voltage and temperature (PVT) influences.

Placement of a clock signal supply network during design of integrated circuits

A representation of a macro for an integrated circuit layout. The representation may define sub-circuit cells of a module. The module may have a predefined functionality. The sub-circuit cells may include at least one reusable circuit cell. The reusable circuit cell may be configured such that when the predefined functionality of the module is not used, the reusable circuit cell is available for re-use.

Growing community of inventors

Munich, Germany

Claus Pribbernow