Infineon Technologies Ag

Infineon Technologies Dresden Gmbh

Infineon Technologies Austria Ag

Claus Dahl

Dmitri Alex Tschumakow

Armin Tilke

Erhard Landgraf

Henning Feick

Thomas Bertrams

Steffen Rothenhaeusser

Andreas Pribil

Wolfram Langheinrich

Knut Stahrenberg

Christoph Wilbertz

Karl-Heinz Mueller

Cajetan Wagner

Siegmar K&ouml;ppe

A method of producing a quantum conveyor includes: forming a pair of screening gate electrodes in or on a semiconductor substrate and that extend between a first stationary quantum dot and a second stationary quantum dot, the pair of screening gate electrodes configured to delimit a channel of moveable quantum dots between the first stationary quantum dot and the second stationary quantum dot; forming, via a lithography process, a plurality of first planar transfer electrodes above the semiconductor substrate and that extend transverse to the channel of moveable quantum dots; and forming, via a self-aligned damascene process, a plurality of second planar transfer electrodes laterally interleaved with the first planar transfer electrodes, wherein the first planar transfer electrodes and the second planar transfer electrodes are configured to transfer quantum information between the first stationary quantum dot and the second stationary quantum dot through the channel of moveable quantum dots.

Quantum conveyor and methods of producing a quantum conveyor

A method for manufacturing a combined semiconductor device. The method includes providing a semiconductor substrate, providing a protective layer or a protective layer stack in a non-CMOS area of the semiconductor substrate, wherein the non-CMOS area is portion of the semiconductor substrate reserved for a non-CMOS device, at least partially manufacturing a CMOS device in a CMOS area of the semiconductor substrate, the non-CMOS area and the CMOS area being different from each other, removing the protective layer or the protective layer stack, to expose the semiconductor substrate in the non-CMOS area, and manufacturing a non-CMOS device in the non-CMOS area of the semiconductor substrate.

Manufacturing a combined semiconductor device

A semiconductor chip may include high frequency electrical circuitry. The semiconductor chip may include a cavity resonator integrated with the high frequency electrical circuitry in a semiconductor substrate of the semiconductor chip. The cavity resonator may include a resonator body in a cavity in the semiconductor substrate of the semiconductor chip. The resonator body may comprise a metal layer. The cavity resonator may include a feeding structure electrically connected to the high frequency electrical circuitry.

On-chip integrated cavity resonator

A bipolar transistor is described. In accordance with one aspect of the present invention the bipolar transistor comprises a semiconductor body including a collector region and a base region arranged on top of the collector region. The base region has a first crystalline structure and is at least partly doped with dopants of a first doping type. The collector region is laterally enclosed by a trench isolation and is doped with dopants of a second doping type. The transistor further comprises a conductive base contact layer laterally enclosing the base region which is doped with dopants of the first doping type. The base contact layer comprises a part with the first crystalline structure and a part with a second crystalline structure, wherein the part with the second crystalline structure laterally encloses the part with the first crystalline structure. The transistor further comprises an emitter region arranged on the base region, wherein the emitter region is doped with dopants of the second doping type and forming a pn-junction with the base region.

Bipolar transistor

A method for manufacturing includes providing a semiconductor substrate having a semiconductor device including at least two device layers to be contacted. A first device layer is smaller than a lithographic minimum feature size used for manufacturing the semiconductor device. Further, the method includes providing an isolation layer on the semiconductor device such that the semiconductor device is covered by the isolation layer; planarizing the isolation layer up to the semiconductor device; providing a first lithographic mask on the semiconductor device, such that the first device layer and a portion of the isolation layer are covered by the first lithographic mask; selectively removing the isolation layer to expose a second device layer while maintaining the portion of the isolation layer that is covered by the first lithographic mask; and providing a stop layer on the first device layer, the second device layer and the portion of the isolation layer.

Method for manufacturing etch stop areas for contacting semiconductor devices

Methods for manufacturing a bipolar junction transistor are provided. A method includes providing a semiconductor substrate having a trench isolation, where a pad resulting from a manufacturing of the trench isolation is arranged on the semiconductor substrate, providing an isolation layer on the semiconductor substrate and the pad such that the pad is covered by the isolation layer, removing the isolation layer up to the pad, and selectively removing the pad to obtain an emitter window.

Heterojunction bipolar transistor fully self-aligned to diffusion region with strongly minimized substrate parasitics and selective pre-structured epitaxial base link

A transistor comprising a semiconductor substrate comprising a collector region extending from a main surface of the semiconductor substrate into a substrate material. The transistor comprising a base structure arranged at the collector region along a thickness direction parallel to a direction of a normal of the main surface of the semiconductor substrate, where an emitter structure arranged at the base structure is averted from the semiconductor substrate and along the thickness direction. The transistor comprising a doped electrode layer arranged at a lateral surface region of the base structure and along a lateral direction perpendicular to the thickness direction. The doped electrode layer and the base structure form a monocrystalline connection.

Transistor having a monocrystalline connection

A bipolar transistor comprises a semiconductor body including a collector region and a base region arranged on top of the collector region. The base region has a first crystalline structure and is at least partly doped with dopants of a first doping type. The collector region is laterally enclosed by a trench isolation and is doped with dopants of a second doping type. The transistor further comprises a conductive base contact layer laterally enclosing the base region which is doped with dopants of the first doping type. The base contact layer comprises a part with the first crystalline structure and a part with a second crystalline structure, wherein the part with the second crystalline structure laterally encloses the part with the first crystalline structure. The transistor further comprises an emitter region arranged on the base region.

A method for manufacturing a bipolar junction transistor is provided. A layer stack is provided that comprises a semiconductor substrate having a trench isolation; an isolation layer arranged on the semiconductor substrate, wherein the first isolation layer comprises a recess forming an emitter window; lateral spacers arranged on sidewalls of the emitter window; a base layer arranged in the emitter window on the semiconductor substrate; and an emitter layer arranged on the isolation layer, the lateral spacers and the base layer. A sacrificial layer is provided on the emitter layer thereby overfilling a recess formed by the emitter layer due to the emitter window. The sacrificial layer is selectively removed up to the emitter layer while maintaining a part of the sacrificial layer filling the recess of the emitter layer. The emitter layer is selectively removed up to the isolation layer while maintaining the filled recess of the emitter layer.

Method for manufacturing an emitter for high-speed heterojunction bipolar transistors

A method comprises arranging a stack, on a semiconductor substrate, comprising a sacrificial layer and an insulating layer. The insulator layer is at least partially arranged between the semiconductor substrate and the sacrificial layer. A recess is formed within the stack. The recess extends through the stack to the semiconductor substrate so that the recess at least partially overlaps with a surface of the collector region of the semiconductor substrate. The collector region extends from a main surface of the semiconductor substrate into the substrate material. The method further comprises generating a base structure at the collector region and in the recess. The base structure contacts and covers the collector region within the recess of the sacrificial layer. The method further comprises generating an emitter structure at the base structure. The emitter structure contacts and at least partially covers the base structure within the recess of the sacrificial layer.

Method for manufacturing a transistor

According to various embodiments, a semiconductor structure may include: a first source/drain region and a second source/drain region; a body region disposed between the first source/drain region and the second source/drain region, the body region including a core region and at least one edge region at least partially surrounding the core region; a dielectric region next to the body region and configured to limit a current flow through the body region in a width direction of the body region, wherein the at least one edge region is arranged between the core region and the dielectric region; and a gate structure configured to control the body region; wherein the gate structure is configured to provide a first threshold voltage for the core region of the body region and a second threshold voltage for the at least one edge region of the body region, wherein the first threshold voltage is less than or equal to the second threshold voltage.

Semiconductor structure and a method for processing a carrier

According to various embodiments, a bipolar transistor structure may include: a substrate; a collector region in the substrate; a base region disposed over the collector region, an emitter region disposed over the base region; a base terminal laterally electrically contacting the base region, wherein the base terminal includes polysilicon.

Bipolar transistor structure and a method of manufacturing a bipolar transistor structure

A transistor component includes an active transistor region arranged in the semiconductor body. And insulation region surrounds the active transistor region in the semiconductor body in a ring-shaped manner. A source zone, a drain zone, a body zone and a drift zone are disposed in the active transistor region. The source zone and the drain zone are spaced apart in a lateral direction of the semiconductor body and the body zone is arranged between the source zone and the drift zone and the drift zone is arranged between the body zone and the drain zone. A gate and field electrode is arranged over the active transistor region. The dielectric layer has a first thickness in a region near the body zone and a second thickness in a region near the drift zone.

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Dresden, Germany

Claus Dahl