Cadence Design Systems, Inc.

Jasper Design Automation, Inc.

Claudionor Jose Nunes Coelho

Lawrence Loh

Victor Markus Purri

Caio Araújo Teixeira Campos

Magnus Björk

Chung-Wah Norris Ip

Thiago Radicchi Roque

A formal verification approach verifies data access and data propagation paths in a circuit design by proving the unreachability of path cover properties of the circuit design. A security path verification system receives an original circuit model of a circuit design, along with parameters identifying a first location within the circuit design that is a source of tainted data and a second location within the circuit design that is coupled to the first location. The security path verification system also receives a selection of portions of the circuit design to be excluded from the verification analysis. Using an abstracted version of the exclude portions, the security verification system generates a second circuit model of the circuit design for use in determining whether the tainted data can reach the second location from the first location within the circuit design.

Security data path verification

Disclosed are techniques for implementing trace warping for electronic designs. These techniques identify a portion of an electronic design including a set of signals of interest corresponding to a plurality of simulation combinations over a range of clock cycles in a trace display. A pair of matching simulation combinations is identified from one or more pairs of matching simulation combinations for the set of signals of interest; and a first clock cycle and a second clock cycle corresponding to the pair of matching simulation combinations are identified in the range of clock cycles. A plurality of clock cycles between the first clock cycle and the second clock cycle can be compressed in the trace display.

Methods, systems, and articles of manufacture for trace warping for electronic designs

Growing community of inventors

Menlo Park, CA, United States of America

Claudionor Jose Nunes Coelho