Nxp USA, Inc.

Intel Corporation

Nxp B.v.

Freescale Semiconductor,inc.

Fujitsu Semiconductor Limited

Claudio Gustavo Rey

David B Harnishfeger

Raja Venkatesh Tamma

Khurram Waheed

Mihai-Ionut Stanciu

Daniel B Schwartz

George Norris

Stefano Dal Toso

Mathieu Perin

Jeffrey D Ganger

Joseph Staudinger

Bing Xu

Mark Alan Kirschenmann

Darin Nguyen

Jau Horng Chen

Samuel Becqué

A type I phase locked loop (PLL) includes an oscillator and a feedback path to a phase detector. A first frequency and first relative phase of a first output signal are locked to a frequency and a phase of a first input signal. A second frequency and second relative phase of a second output signal are locked to a frequency and a phase of a second input signal. A correction to the PLL is applied to perform one of: adjusting the second relative phase to equal the first relative phase and adjusting the oscillator frequency.

Type-I PLLs for phase-controlled applications

A method for estimating a time-of-arrival of a packet received by a receiver includes storing a reference bit-pattern and receiving a plurality of samples in a samples-buffer. In a bit-pattern detector, a matching group of samples having a bit-pattern which matches the reference bit-pattern is identified. In a correlator, a group of three correlation values is determined from the matching group of samples, including a local maximum correlation value, P0, an immediately preceding correlation value, Pm, and an immediately succeeding correlation value Pp. In an estimation unit, a polynomial function f(&#x3b4;) of the difference, &#x3b4;, between Pm and Pp is used to estimate a timing offset T, between the local maximum correlation value and a correlation peak. The time-of-arrival is estimated from a time of the local maximum correlation value P0, and T.

Methods and apparatus for estimating a time-of-arrival or a distance between two device

A type I phase locked loop (PLL) includes an oscillator and a feedback path to a phase detector. The PLL is configured to lock a first frequency and first relative phase of a first output signal to a frequency and a phase of a first input signal, and lock a second frequency and second relative phase of a second output signal to a frequency and a phase of a second input signal. A steady state phase lag of the PLL resulting from the difference between the first frequency and the second frequency is estimated, and the estimated steady state phase lag is used to determine a total phase shift (&#x394;&#x3a6;) between the second input signal and the second output signal. The PLL for the phase shift can be compensated. The determined total phase shift can be used in a distance estimation.

An acquisition detector and method include a preamble detector configured to search in a plurality of symbols for a preamble match with a known preamble pattern when a power level of the input signal exceeds a determined noise threshold. The acquisition detector further includes a frame delimiter detector configured to search in the plurality of symbols for a frame delimiter match with a known frame delimiter pattern when the preamble match is identified and the power level of the input signal exceeds a determined noise threshold.

Acquisition of a data packet having a short preamble

An arbitrary rate digital decimator filter () and associated method are disclosed for filtering a digital data stream with a plurality of cascaded power-of-two decimator stages () connected to receive the digital data stream and to generate a first filtered digital signal which is provided to a fractional resampling stage () which generates a second filtered digital signal with delta-sigma modulator () and a limited integrator stage () connected to receive a first control () word and a feedback clock signal () with inserted or swallowed pulses which is generated by a clock generator in response to pulse commands generated by the limited integrator stage, wherein the limited integrator is configured to generate time shift commands () to a timing shift filter () which performs fractional interpolation on the first filtered digital signal to generate the second filtered digital signal.

Arbitrary rate decimator and timing error corrector for an FSK receiver

The embodiments described herein provide systems and methods for digital correction in low intermediate frequency (IF) receivers. Specifically, the embodiments described herein use digital correction techniques that can correct for signal distortions in low IF receivers caused by I-Q imbalance, including both I-Q magnitude imbalance and I-Q phase imbalance. In general, the embodiments described herein are implemented to at least partially cancel an image of a blocking signal in the complex digital signal. Such a cancellation can be implemented to at least partially cancel an image of blocking signal where that image occurs at or near the intermediate frequency. In one embodiment, a corrector is implemented in a low RF receiver and is configured to receive a complex digital signal that includes an image of a blocking signal. Such a low RF receiver can further include a trainer configured to train the corrector to generate the cancellation signal.

Systems and methods for digital correction in low intermediate frequency (IF) receivers

The embodiments described herein provide systems and methods for digital correction in low intermediate frequency (IF) receivers. Specifically, the embodiments described herein use digital correction techniques that can correct for signal distortions in low IF receivers caused by I-Q imbalance, including both I-Q magnitude imbalance and I-Q phase imbalance. In general, the embodiments described herein are implemented to at least partially cancel an image of a blocking signal in the complex digital signal. Such a cancellation can be implemented to at least partially cancel an image of blocking signal where that image occurs at or near the intermediate frequency. In one embodiment, a corrector is implemented in a low RF receiver and is configured to receive a complex digital signal that includes an image of a blocking signal. Such a low RF receiver can further include a corrector controller to selectively enable the corrector.

Systems and methods for digital correction with selective enabling in low intermediate frequency (IF) receivers

A demodulator and method includes a plurality of correlation circuits, a result combining stage, and a time combining stage. The plurality of correlation circuits may be configured to output a plurality of correlation values that indicate a likelihood of whether a pattern of a buffered portion of an input data signal matches a first plurality of target frequency behavior patterns. The plurality of correlation circuits may be further configured to output a plurality of delayed correlation values that indicate a likelihood of whether a pattern of a delayed buffered portion of the input data signal matches a second plurality of target frequency behavior patterns, where both the buffered portion and the delayed buffered portion include a current symbol.

Symbol demodulator with error reduction

A preamble detection system and method includes converting the phase domain input samples corresponding to the preamble into frequency domain input samples. An I/Q-formatted dot product is generated from a dot product process between the frequency domain input samples and a reference pattern indicative of an expected preamble. The I/Q-formatted dot product is averaged with at least one previously generated I/Q-formatted dot product to generate an I/Q-formatted averaged dot product. The I/Q-formatted averaged dot product is converted into a polar-formatted averaged dot product, wherein the polar-formatted averaged dot product includes a magnitude of the polar-formatted averaged dot product and an angle of the polar-formatted averaged dot product. A preamble-found signal is then generated in response to the magnitude of the polar-formatted averaged dot product exceeding a preamble magnitude threshold.

Preamble detection during acquisition

A method includes, at a frequency shift keying (FSK) demodulator, determining a likelihood of a symbol having a first symbol value or a second symbol value, using the likelihood of the symbol to select either the first symbol value or the second symbol value for the symbol, the first symbol value or the second symbol value that is selected being a selected symbol value, selecting a frequency error from a first frequency error or a second frequency error, and using a down-mixer and the frequency error to correct a frequency drift associated with a future selected symbol value.

Frequency shift keying (FSK) error detector and method therefor

A frame delimiter detection system and method includes a phase differentiator and buffering module, a phase-to-I/Q reformatting module, a dot product module, an I/Q-to-polar reformatting module, a dot product comparison module, and a frame delimiter detection module. The method may include receiving in-phase and quadrature-phase (I/Q) formatted frequency domain input samples configured as a frame delimiter in a communication packet. An I/Q formatted dot product may be generated from the I/Q formatted frequency domain input samples and a reference pattern indicative of an expected frame delimiter. Further, a frame delimiter detection signal may be generated based on a magnitude of the I/Q formatted dot product.

Frame delimiter detection

A method of operating frequency shift keying (FSK) demodulator for demodulating symbols includes providing current and previous buffered portions of an input signal to correlation circuits of the FSK demodulator, where each buffered portion persists for a symbol duration time period. The correlation circuits output first correlation metrics that indicate a likelihood of whether the buffered portions match a respective target pattern. The first correlation metrics are combined into a set of first correlation results, which are delayed by at least the symbol duration time period. The current and next buffered portions are provided to the correlation circuits, which output second correlation metrics that are combined into a set of second correlation results. The set of second correlation results are combined with the delayed set of first correlation results to produce a demodulation decision that indicates a most likely symbol value encoded in the current buffered portion.

Frequency shift keying (FSK) demodulator and method therefor

A method and apparatus for identifying a search window of carrier-frequency-offset-corrected samples in which a first intermediate signal from a demodulator does not exceed a predetermined threshold, convolving a second intermediate signal from the demodulator within the search window with a predefined pattern to provide a convolution result, determining if an absolute peak of the convolution result exceeds a preamble pattern confirmation threshold, in response to the absolute peak of the convolution result exceeding the preamble confirmation threshold, confirming a preamble pattern detection event to provide a confirmed preamble pattern detection event of a confirmed preamble pattern, and receiving a signal including the confirmed preamble pattern to provide a received digital signal extracted from the signal.

Tone rejection during synchronization in frequency shift keyed modulation systems

A frequency shift keying (FSK) demodulator for demodulating symbols includes correlation circuits configured to output correlation metrics based on a buffered portion of an input signal as the input signal is continuously received by the FSK demodulator. The FSK demodulator also includes a result combining stage configured to output a set of first correlation results based on correlation metrics generated for a first portion of the input signal encoding a current symbol and at least one past symbol, and a set of second correlation results based on correlation metrics generated for a second portion of the input signal encoding the current symbol and at least one next symbol; and a time combining stage configured to combine a set of delayed first correlation results with the set of second correlation results to produce a demodulation decision that returns a most likely symbol value for the current symbol.

A circuit may include a digitally-controlled oscillator including a coarse frequency-tuning array with a multiple selectable coarse frequency-tuning segments. Each of the coarse frequency-tuning segments may have a coarse segment frequency step size. The digitally-controlled oscillator may also include a fine frequency-tuning array with multiple selectable fine frequency-tuning segments. The fine frequency-tuning array may have a fine array frequency step size that is at least twice the coarse segment frequency step size. The digitally-controlled oscillator may be configured to generate an output signal with a frequency based on the coarse frequency-tuning array and the fine frequency-tuning array.

Growing community of inventors

Chandler, AZ, United States of America

Claudio Gustavo Rey