Kabushiki Kaisha Toshiba

Claudio Fiegna

Hiroshi Iwai

Masanobu Saito

Yukihiro Ushiku

Mizuki Ono

Satoshi Matsuda

Yasushi Akasaka

Hisayo S Momose

Takashi Yoshitomi

Yasuhiro Katsumata

Hideaki Nii

Tatsuya Ooguro

A MOS type semiconductor device has a gate whose length is 170 nm (0.17 .mu.m) or less, a junction depth of source and drain diffusion layers in the vicinity of a channel is 22 nm or less, and a concentration of impurities at the surface in the source and drain diffusion layers is made to 10.sup.20 cm.sup.-3 or more. Such structure is obtained using solid phase diffusion using heat range from 950.degree. C. to 1050.degree. C. and/or narrowing gate width by ashing or etching. The other MOS type semiconductor device is characterized in that the relationship between the junction depth x.sub.j �nm! in the source and drain diffusion layer regions and the effective channel length L.sub.eff �nm! is determined by L.sub.eff &gt;0.69 x.sub.j -6.17.

MOSFET with solid phase diffusion source

Growing community of inventors

Bologna, Italy

Claudio Fiegna