Sgs-thomson Microelectronics S.r.l.

Sgs Microelettronica Spa

Stmicroelectronics S.r.l.

Sgs-thomson Microelectronics S.p.a.

Claudio Contiero

Paola Galbiati

Antonio Andreini

Lucia Zullino

Bruno Murari

Riccardo Depetro

Michele Palmieri

Stefano Manzini

Tiziana Cavioni

Ubaldo Mastromatteo

Claudio Diazzi

Franco Bertotti

Carlo Cini

Fabrizio Fausto Renzo Toia

Simone Dario Mariani

Giorgio De Santi

Elisabetta Pizzi

Giulio Iannuzzi

Fabrizio Andreani

Riccardo De Petro

Luica Zullino

A semiconductor device includes: a semiconductor body including an active region that houses an electronic component and a passive dielectric region surrounding the active region; a conductive buried region, of metallic material or metallic alloy, which extends in the semiconductor body in the active region; and one or more electrical contacts, of metallic material, which extend between the conductive buried region and a top surface of the semiconductor body, and form respective paths for electrical access to the conductive buried region.

Semiconductor device with buried metallic region, and method for manufacturing the semiconductor device

Complementary LDMOS and MOS structures and vertical PNP transistors capable of withstanding a relatively high voltage may be realized in a mixed-technology integrated circuit of the so-called &ldquo;smart power&rdquo; type, by forming a phosphorus doped n-region of a similar diffusion profile, respectively in: The drain zone of the n-channel LDMOS transistors, in the body zone of the p-channel LDMOS transistors forming first CMOS structures; in the drain zone of n-channel MOS transistors belonging to second CMOS structures and in a base region near the emitter region of isolated collector, vertical PNP transistors, thus simultaneously achieving the result of increasing the voltage withstanding ability of all these monolithically integrated structures. The complementary LDMOS structures may be used either as power structures having a reduced conduction resistance or may be used for realizing CMOS stages capable of operating at a relatively high voltage (of about 20V) thus permitting a direct interfacing with VDMOS power devices without requiring any &ldquo;level shifting&rdquo; stages. The whole integrated circuit has less interfacing problems and improved electrical and reliability characteristics.

Mixed technology integrated device comprising complementary LDMOS power transistors, CMOS and vertical PNP integrated structures having an enhanced ability to withstand a relatively high supply voltage

A high-voltage lateral MOSFET transistor structure constituted by various interdigitated modular elements formed on a layer of monocrystaline silicon is described together with a process for its fabrication. To save area of silicon and to reduce the specific resistivity RDS on doping drain regions are formed by implanting doping material in the silicon through apertures in the field oxide obtained with a selective anisotropic etching by utilizing as a mask the strips of polycrystaline silicon which serve as gate electrodes and field electrodes.

Process for fabricating a high voltage MOSFET

A process for the manufacturing of an integrated circuit having DMOS-technology power devices and non-volatile memory cells provides for forming respective laterally displaced isolated semiconductor regions, electrically insulated from each other and from a common semiconductor substrate, inside which the devices will be formed; forming conductive gate regions for the DMOS-technology power devices and for the memory cells over the respective isolated semiconductor regions. Inside the isolated semiconductor regions for the DMOS-technology power devices, channel regions extending under the insulated gate regions are formed. The channel regions are formed by an implantation of a dopant along directions tilted of a prescribed angle with respect to a direction orthogonal to a top surface of the integrated circuit, in a dose and with an energy such that the channel regions are formed directly after the implantation of the dopant without performing a thermal diffusion at a high temperature of the dopant.

Process for the manufacturing of integrated circuits comprising

N-channel LDMOS and p-channel MOS devices for high voltage integrated in a BiCMOS integrated circuit and exploiting a RESURF condition are provided with a buried region of the same type of conductivity of the epitaxial layer and a doping level intermediate between the doping level of the epitaxial layer and the doping level of a well region. The devices may be configured as source or drain followers without problems.

Thin epitaxy resurf integrated circuit containing high voltage p-channel

An integrated circuit structure is disclosed wherein an EPROM cell has an active area formed by the same operations as are carried out to form a P region intended to contain an N-channel MOS transistor, source and drain regions formed by the same operations as are carried out to form the source and drain regions of said transistor, a control electrode consisting of an N+ region formed by the same operations as are carried out to form deep regions intended to contact buried N+ regions, and a floating gate electrode consisting of a layer of conductive material formed by the same operations as are carried out to form the gate electrodes of the MOS transistors in the integrated circuit. The EPROM cell can, therefore, be formed in a mixed integrated circuit with no need for purposely added processing steps.

Integrated circuit with EPROM cells

The resin sealing layer enclosing the device is biased to a low voltage by means of an anchoring structure formed close to high-voltage contact pads. The anchoring structure is formed by a metal region deposited on the surface of the device and contacting the resin layer, and by a deep region extending from the surface of the device, beneath the metal region, to the substrate. The electrical field in the resin layer is confined between the high-voltage pads and the anchoring structure and prevented from generating polarity inversions in the semiconductor material at the low-voltage contact pads or any other points at which the resin layer contacts the body of semiconductor material.

Surface electrical field delimiting structure for an integrated circuit

An integrated device including a structure for protection against electric fields. The protection structure may include a first region of conducting material electrically connected to the gate/source region of the device at a first potential. The protection structure may also include a second region of conducting material electrically connected to the drain region of the device at a second potential differing from the first. In one embodiment, the first region of conducting material is comb-shaped, and includes a first number of fingers separated by a plurality of gaps. The second region of conducting material includes portions extending at the aforementioned gaps to form a comb structure. Thus, the body of semiconductor material of the device sees a protection region formed by a pair of interlocking comb structures at an intermediate potential between the first and second potentials.

Integrated device with a structure for protection against high electric

The breakdown voltage of a VDMOS transistor is markedly increased without depressing other electrical characteristics of the device by tying the potential of a field-isolation diffusion, formed under the edge portion of a strip of field oxide separating a matrix of source cells from a drain diffusion, to the source potential of the transistor. This may be achieved by extending a body region of a peripheral source cell every given number of peripheral cells facing the strip of field-isolation structure until it intersects said field-isolation diffusion. By so connecting one peripheral source cell every given number of cells, the actual decrement of the overall channel width of the integrated transistor is negligible, thus leaving unaltered the electrical characteristics of the power transistor.

Method for fabricating VDMOS transistor with improved breakdown

VDMOS transistor with improved breakdown characteristics

An integrated circuit self-protected against a reversal of its supply battery polarity comprises a first DMOS power transistor connected with its source electrode side to an electric load to be driven toward ground, and a second, protective DMOS transistor which is connected with its source electrode side to a positive pole of the battery and with its drain electrode side to the drain electrode of the first transistor. The first and second transistors have in common the drain region formed on a single pod in the semiconductor substrate.

Integrated circuit self-protected against reversal of the supply battery

A high density, mixed technology integrated circuit comprises CMOS structures and bipolar lateral transistors, the electrical efficiency and Early voltage of which are maintained high by forming 'well' regions through the collector area. The operation determines the formation of a 'collector extension region' extending relatively deep within the epitaxial layer so as to intercept the emitter current and gather it to the collector, subtracting it from dispersion toward the substrate through the adjacent isolation junctions surrounding the region of the lateral bipolar transistor. Under comparable conditions, the ratio between IcIsubstrate is incremented from about 8 to about 300 and the Early voltage from about 20V to about 100V. The V.sub.CEO, BV.sub.CBO and BV.sub.CDES voltages are also advantageously increased by the presence of said 'well' region formed in the collector zone.

Mixed technology integrated circuit comprising CMOS structures and

Complementary LDMOS and MOS structures and vertical PNP transistors capable of withstanding a relatively high voltage may be realized in a mixed-technology integrated circuit of the so-called 'smart power' type, by forming a phosphorus doped n-region of a similar diffusion profile, respectively in: The drain zone of the n-channel LDMOS transistors, in the body zone of the p-channel LDMOS transistors forming first CMOS structures; in the drain zone of n-channel MOS transistors belonging to second CMOS structures and in a base region near the emitter region of isolated collector, vertical PNP transistors, thus simultaneously achieving the result of increasing the voltage withstanding ability of all these monolithically integrated structures. The complementary LDMOS structures may be used either as power structures having a reduced conduction resistance or may be used for realizing CMOS stages capable of operating at a relatively high voltage (of about 20V) thus permitting a direct interfacing with VDMOS power devices without requiring any 'level shifting' stages. The whole integrated circuit has less interfacing problems and improved electrical and reliability characteristics.

Mixed technology integrated device comprising complementary LDMOS power

This method, requiring a reduced number of process phases and providing an efficient, high-voltage structure, comprises forming a P-well region of the N-channel transistor of a CMOS device, by means of boron atom implant through a protective mask, forming at least one insulation region surrounding the CMOS device, forming edge regions having the same conductivity type as the insulation region but with a smaller concentration of impurities on at least one part of the insulation region and in the high-voltage electronic devices by means of the same boron atom implant used to form the P-well region.

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Buccinasco, Italy

Claudio Contiero