Stmicroelectronics S.r.l.

Sgs-Thomson Microelectronics S.r.l.

Claudio Brambilla

Manlio Sergio Cereda

Paolo Caprara

Giancarlo Ginami

Andrea Ravaglia

Stefano Daffra

Sergio Manlio Cereda

Valerio Cassio

Rustom Irani

Manlio Sergio Creda

Pierantonio Pozzoni

A process for manufacturing a dual charge storage location electrically programmable memory cell that includes the steps of forming a central insulated gate over a semiconductor substrate; forming physically separated charge-confining layers stack portions of a dielectric-charge trapping material-dielectric layers stack at the sides of the central gate, the charge trapping material layer in each charge-confining layers stack portion forming a charge storage element; forming side control gates over each of the charge-confining layers stack portions; forming memory cell source/drain regions laterally to the side control gates; and electrically connecting the side control gates to the central gate. Each of the charge-confining layers stack portions at the sides of the central gate is formed with an 'L' shape, with a base charge-confining layers stack portion lying on the substrate surface and an upright charge-confining layers stack portion lying against a respective side of the insulated gate.

Process for manufacturing a dual charge storage location memory cell

A process for manufacturing a dual charge storage location electrically programmable memory cell that includes the steps of forming a central insulated gate over a semiconductor substrate; forming physically separated charge-confining layers stack portions of a dielectric-charge trapping material-dielectric layers stack at the sides of the central gate, the charge trapping material layer in each charge-confining layers stack portion forming a charge storage element; forming side control gates over each of the charge-confining layers stack portions; forming memory cell source/drain regions laterally to the side control gates; and electrically connecting the side control gates to the central gate. Each of the charge-confining layers stack portions at the sides of the central gate is formed with an &ldquo;L&rdquo; shape, with a base charge-confining layers stack portion lying on the substrate surface and an upright charge-confining layers stack portion lying against a respective side of the insulated gate.

A process for manufacturing electronic semiconductor integrated memory devices having a virtual ground and comprising at least a matrix of floating gate memory cells is presented. In the memory device, the matrix is formed on a semiconductor substrate with a number of continuous bit lines extending across the substrate as discrete parallel strips. The process begins by growing an oxide layer over the matrix region and depositing over the semiconductor throughout a stack structure which comprises a first conductor layer, a first dielectric layer, and a second conductor layer. Then a second dielectric layer is deposited over the stack structure, and floating gate regions are defined by photolithography using a mask of &ldquo;POLY along a first direction&rdquo;, to thereby define in the dielectric layer, a plurality of parallel strips which delimit a first dimension of floating gate regions. Next the dielectric layer is etched away to define a plurality of parallel dielectric strips and a number of dielectric islands are defined by photolithography using a mask of &ldquo;POLY along a second direction&rdquo; in the plurality of parallel strips. The dielectric layer is etched to define the plurality of islands. Finally, the stack structure and the thin gate oxide layer are etched to define gate regions of the matrix cells using said oxide island.

Process for manufacturing semiconductor integrated memory devices with cells matrix having virtual ground

A process for manufacturing an integrated circuit comprising an array of memory cells, providing for: a) forming in a memory cell array area of a semiconductor layer ( ) an active area for the memory cells; b) forming over said active area for the memory cells a gate oxide layer ( ); c) forming over the whole integrated circuit a first layer of conductive material ( ); d) forming over the first layer of conductive material ( ) a layer of insulating material ( ); e) removing the layer of insulating material ( ) from outside the memory cell array area; f) forming over the whole integrated circuit a second layer of conductive material ( ) which in the memory cell array area is separated from the first layer of conductive material ( ) by the insulating material layer ( ), while outside the memory cell array area is directly superimposed over said first layer of conductive material ( ); g) inside the memory cell array area, defining first strips ( ) of the second layer of conductive material ( ) for forming rows ( ) of the memory cell array ( ), and outside the memory cell array area defining second strips ( ) of the second layer of conductive material ( ) for forming interconnection lines ( ) for electrically interconnecting the rows ( ) of the memory cell array with a circuitry ( RD), said defining the second strips ( ) providing for selectively etching the first and second layers of conductive material ( ) outside the memory cell array area by means of a first mask (MASK ), and said defining the first strips ( ) providing for selectively etching the second layer of conductive material ( ), the layer of insulating material ( ) and the first layer of conductive material ( ) inside the memory cell array area by means of a second mask (MASK ).

Process for manufacturing an integrated circuit comprising an array of memory cells

A method for autoaligning lines of a conductive material in circuits integrated on a semiconductor substrate is presented. The method includes forming several regions projecting from the substrate surface and aligned to one another, and forming a fill layer in the gaps between the projecting regions. The fill layer is planarized to expose the regions, and a portion of the regions is removed to form holes at the locations of the regions. Next an insulating layer is formed in the holes. The insulating layer is selectively removed to form spacers along the edges of said holes and at least one conductive layer is deposited over the exposed surface. Later, a step of photolithograpy with a mask is performed and the conductive layer is etched to define lines and collimate them to the underlying regions.

Method for autoaligning overlapped lines of a conductive material in integrated electronic circuits

A method of manufacturing a semiconductor virtual ground memory device having a matrix of floating gate memory cells formed on a semiconductor substrate with a plurality of continuous bit lines extending across the substrate as discrete parallel stripes. The device also includes a circuit portion for selection transistors and decode and address circuit portions having P-channel and N-channel MOS transistors. According to the method, N-wells are formed in at least one substrate portion to accommodate the P-channel transistors, active areas of all transistors are defined using a screening mask, and then an isolation layer is grown through the apertures of the screening mask. The screening mask is not open over the matrix region of the memory cells.

Method of manufacturing an EPROM memory device having memory cells organized in a tablecloth matrix

A process for manufacturing electronic semiconductor integrated electronic memory devices having virtual ground and including at least a matrix of floating gate memory cells formed on a semiconductor substrate with a plurality of continuous bit lines extending across the substrate as discrete parallel strips begins with forming an oxide layer over the matrix region. Then, the semiconductor throughout is deposited with a stack structure which includes a first conductor layer, a first dielectric layer, and second conductor layer. Next, a second dielectric layer is formed. Floating gate regions are defined by photolithography using a mask of &ldquo;POLY,along a first predetermined direction&rdquo;, and associated etching, to define, in the stack structure, a plurality of parallel openings. These openings are implanted to confer a predetermined conductivity on the bit line regions. Next, the parallel openings are filled with a photo-sensitive material to protect the matrix bit lines.

A process for manufacturing a MOS transistor and especially a MOS transistor used for non-volatile memory cells is presented. At the start of the manufacturing, a semiconductor substrate having a first type of conductivity is covered by a gate oxide layer. A gate electrode is formed over the gate oxide layer, which is a stacked gate when the MOS transistor is used in a non-volatile memory. Covering the gate electrode is a covering oxide that is formed over the gate oxide layer, the gate electrode, and around the gate electrode. Next, a dopant of a second type of conductivity is implanted to provide implant regions adjacent to the gate electrode. Subjecting the semiconductor to thermal treatments allows the implanted regions to diffuse into the semiconductor substrate under the gate electrode and form a gradual junction drain and source region of the MOS transistor.

Method for forming contactless MOS transistors and resulting devices, especially for use in non-volatile memory arrays

A method for improving the intermediate dielectric profile, particularly for non-volatile memories constituted by a plurality of cells, including the following steps: forming field oxide regions and drain active area regions on a substrate; forming word lines on the field oxide regions; depositing oxide to form oxide wings that are adjacent to the word lines; opening, by masking, source regions and the drain active area regions, keeping the field oxide regions that separate one memory cell from the other, inside the memory, covered with resist; and removing field oxide in the source regions and removing oxide wings from both sides of the word lines.

Method for improving the intermediate dielectric profile, particularly

A method is provided of manufacturing a P-channel native MOS transistor in a circuit integrated on a semiconductor which also includes a matrix of non-volatile memory cells of the floating gate type with two polysilicon levels having an interpoly dielectric layer sandwiched between the two polysilicon levels. The method has the following steps: (1) masking and defining active areas of the discrete integrated devices; (2) masking and defining the first polysilicon level using a Poly1 mask; and (3) masking and defining an intermediate dielectric layer using a matrix mask. The length of the native threshold channel of the native transistor is defined by means of the matrix mask and by etching away the interpoly dielectric layer. A subsequent step of masking and defining the second polysilicon level provides for the use of a Poly2 mask which extends the active area of the transistor with a greater width than the previous mask in order to enable, by subsequent etching, the two polysilicon levels to overlap in self-alignment over the channel region.

Method for manufacturing a native MOS P-channel transistor with a

A process for manufacturing an integrated circuit comprising an array of memory cells, providing for: a) forming in a memory cell array area of a semiconductor layer (6) an active area for the memory cells; b) forming over said active area for the memory cells a gate oxide layer (8); c) forming over the whole integrated circuit a first layer of conductive material (9); d) forming over the first layer of conductive material (9) a layer of insulating material (10); e) removing the layer of insulating material (10) from outside the memory cell array area; f) forming over the whole integrated circuit a second layer of conductive material (11) which in the memory cell array area is separated from the first layer of conductive material (9) by the insulating material layer (10), while outside the memory cell array area is directly superimposed over said first layer of conductive material (9); g) inside the memory cell array area, defining first strips (22) of the second layer of conductive material (11) for forming rows (3) of the memory cell array (1), and outside the memory cell array area defining second strips (17) of the second layer of conductive material (11) for forming interconnection lines (100) for electrically interconnecting the rows (3) of the memory cell array with a circuitry (5,RD) said, first strips (22) and the second strips (17) of the second layer of conductive material (11) are automatically joined at respective ends thereof at said boundary region.

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Concorezzo, Italy

Claudio Brambilla