Infineon Technologies Ag

Claudio Andreotti

Anthony Sanders

Edoardo Prete

Method and arrangement for generating an output clock signal with an adjustable phase relation from a plurality of input clock signals. A method and an arrangement are provided for generating an output clock signal (o), in which a plurality of input clock signals (s, c) that have a predetermined phase relationship to one another, are weighted with respective weighting factors (A,-A), and in which the weighted input clock signals (s', c&#x2032;) are added in order to generate a summated clock signal (i). The summated clock signal (i) is integrated in an integrator () and optionally amplified in order to generate the output clock signal (o). An output clock signal (o) with an adjustable phase relation can be generated with such a method and such an arrangement, in which the requirements placed on the input clock signals are less stringent.

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Munich, Germany

Claudio Andreotti