Sensio Technologies Inc.

3dn, LLC

Socovar Sec

Other

The Royal Institution for the Advancement of Learning / Mcgill University

Ecole De Technologie Superieure

Hyperchip Inc.

Socovar, Societe En Commandite

Ecole De Technologies Superieure

Ecole De Technologie Superieure Polyvalor, Limited Partnership

Claude Thibeault

Jean Belzile

Nicholas Routhier

Daniel Malouin

Martin Dallaire

Pierre-Paul Carpentier

Yvon Savaria

François Gagnon

Gabi Sarkis

Warren Jeffrey Gross

Pascal Giard

Yves Blaquiere

Jean-Jacques Laurin

Zhong-Fang Jin

Meng Lu

Philippe Dumais

Mohamed Lassaad Ammari

Karl Fecteau

Naim Batani

A method for decoding a compressed image stream, the image stream having a plurality of frames, each frame consisting of a merged image including pixels from a left image and pixels from a right image. The method involves the steps of receiving each merged image; changing a clock domain from the original input signal to an internal domain; for each merged image, placing at least two adjacent pixels into an input buffer and interpolating an intermediate pixel, for forming a reconstructed left frame and a reconstructed right frame according to provenance of the adjacent pixels; and reconstructing a stereoscopic image stream from the left and right image frames. The invention also teaches a system for decoding a compressed image stream.

Process and system for encoding and playback of stereoscopic video sequences

There is described a multi-mode unrolled decoder. The decoder comprises a master code input configured to receive a polar encoded master code of length N carrying k information bits and N&#x2212;k frozen bits, decoding resources comprising processing elements and memory elements connected in an unrolled architecture and defining an operation path between the master code input and an output, for decoding a polar encoded code word, at least one constituent code input configured to receive a polar encoded constituent code of length N/p carrying j information bits and N/p&#x2212;j frozen bits, where p is a power of 2, and at least one input multiplexer provided in the operation path to selectively transmit N/p bits of one of the master code and the constituent code to a subset of the decoding resources.

Multi-mode unrolled polar decoders

A method and apparatus is disclosed for performing a multi-equalization of a transmitted signal on a channel having varying characteristics comprising equalizing the transmitted signal using a plurality of setting defining a plurality of equalizing functions to provide a corresponding plurality of symbol signal, synchronizing each of the plurality of symbol signals to provide a plurality of synchronized signals, selecting at least one of the plurality of synchronized signals according to at least one transmission performance criterion and providing the selected one of the plurality of synchronized signals.

Multi-equalization method and apparatus

In a method of data transmission according to one embodiment of the invention, data transitions on adjacent conductors are separated in time. In a method of data transmission according to another embodiment of the invention, signals on adjacent conductive paths pass through different alternating sequences of inversions and regenerations. In a method of data transmission according to a further embodiment of the invention, data transitions having the same clock dependence are separated in space.

Methods, apparatus, and systems for reducing interference on nearby conductors

A method and apparatus is disclosed for testing a reconfigurable logic block. Preferably, this invention is intended to be used with Field Programmable Gate Array. According to the invention, a test bus addressing unit and a test bus activation unit are used to perform a test on a logic block. Upon selection of a corresponding logic block, a test data is outputted on a test bus which enables a testing of the logic function.

Method and apparatus for testing a device in an electronic component

A digital parallelized Infinite Impulse Response (IIR) integrator filter comprising a first channel having a first input and second channel having a second input, a first adder to add the two channel inputs, an integrator to integrate the added channel inputs to provide a first channel output is described herein. The second input channel is adjacent in time to the first channel input. The second channel further comprises a second adder which adds the first output with the second channel input in order to produce a second output, adjacent in time with the first output. This configuration can be generalized to n inputs and m outputs.

Parallelized infinite impulse response (IIR) and integrator filters

A system and method for testing the data propagation time in an integrated circuit at relatively low speed is described herein. The method uses at least two parallel circuits comprising a data circuit and a clock circuit, wherein these parallel circuits are provided with at least one inverter for sensing the feeding current of each circuit so as to obtain current pulses that are transformed into binary signals forwarded to a tester that measures the delay time between these signals.

Integrated circuit testing system and method

A reticle and method simultaneously generate small- and large-scale circuit structures of a parallel processing system. The reticle includes at least two circuit traces having respective contact pads within an overlap zone of the reticle. Connectivity between a circuit trace of one reticle image with a circuit trace of an adjacent reticle image is controlled by varying the degree of overlap between the two images.

Method of generating large scale signal paths in a parallel processing system

A synchronous clocking method and apparatus is disclosed for clocking a plurality of processing units. Each of the plurality of processing units is connected to at least another one using an interblock synchronization signal. Upon receipt of the interblock synchronization signal, data is provided between at least two processing units.

Data driven clocking

Growing community of inventors

Brossard, Canada

Claude Thibeault