Bull Hn Information Systems, Inc.

Claude Rabel

Russell Wayne Guenthner

William A Shelly

Eric Earl Conway

Boubaker Shaiek

Ron Yoder

A processor ( ) in a data processing system simultaneously loads multiple registers ( ) with a single value for fast domain switching. A domain switch instruction asserts a register block write signal ( ) along with the register write signal ( ) when block writing the single value to the set of registers ( ). Register address lines ( ) are decoded in two sets: a first set of decoded address lines ( ) specifying a block of registers; and the second set ( ) specifying one register in the block of registers. When the register block write signal ( ) is asserted during a register write, the second set of decoded address lines ( ) are ignored, and all registers in the block of registers ( ) selected by the first set of decoded address lines ( ) are simultaneously loaded with a common value. Additional drive requirements are solved either by adding a buffer ( ) to each register bit, or by disabling ( ) the feedback path ( ) in each register bit during block writes.

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Phoenix, AZ, United States of America

Claude Rabel