Sun Microsystems, Inc.

Advanced Micro Devices Corporation

Ati Technologies Inc.

Claude R Gauthier

Brian W Amick

Pradeep R Trivedi

Dean Liu

Aninda K Roy

Spencer Montgomery Gold

Gin S Yee

Tyler J Thorp

Lin Chen

Joseph D Macri

Shaishav A Desai

Ming-Ju Edward Lee

Tri K Tran

Stephen L Morein

Kamran Zarrineh

Sudhakar Bobba

Richard L Wheeler

Lynn Warriner

Raymond A Heald

Kenneth Alan House

Lynn Ooi

Gajendra Prasad Singh

Steven R Boyle

Aparna Ramachandran

Steven Morein

Dong Joon Yoon

David J Greenhill

Arvind Bomdica

Joseph Raymond Siegel

Kathirgamar Aingaran

Anup S Mehta

Priya Ananthanarayanan

Siji Menokki Kandiyil

Miriam G Blatt

Sam Huynh

Edward Lee

Hiok-Tiaq Ng

John Ling

Jennifer Ho

Kian Chong

A system and method for detecting errors in high-speed asymmetric interfaces are described. Embodiments include transmitting digital data between a first system component and a second system component over a bidirectional interface, wherein the first component is significantly more intelligent than the second component. The first component receives a signature from the second component over a line of the interface concurrent with READ and WRITE operations over the interface. The latency associated with transmission of a signature from the second component to the first component is the time taken for the second component to compute a signature. The signature received is compared to a signature stored by the first component. Both signatures correspond to a particular READ or WRITE command. Based on the comparison, the first component determines whether the READ or WRITE operation was successful, and directs the second component as necessary.

Error detection in high-speed asymmetric interfaces utilizing dedicated interface lines

A system and method for detecting errors in high-speed asymmetric interfaces are described. Embodiments include transmitting digital data between a first system component and a second system component over a bidirectional interface, wherein the first component is significantly more intelligent than the second component. The first component controls many operations of the second component, including receiving a signature from the second component over an existing line of the interface. The signature received is compared to a signature stored by the first component. Both signatures correspond to a transaction over the interface. Based on the comparison, the first component determines whether the transaction was successful, and directs the second component as necessary.

Error detection in high-speed asymmetric interfaces

An asymmetrical IO method and system are described. In one embodiment, a host device includes shared resources for data synchronization of the host device and a client device. The shared resources include a shared phase interpolator. In an embodiment, data lines between the host and client are also used to transmit phase information from the client device to the host device, obviating the need for additional, dedicated lines or pins.

System and apparatus for transmitting phase information from a client to a host between read and write operations

Embodiments of a power consumption reduction process for memory interfaces are described. A power management process reduces the amount of time that current flows in a high or low terminated, current or voltage mode unipolar bus interface by reducing the amount of time the bus remains in a logic state that requires current flow.

Low power mode unipolar current/voltage mode interface

An IO method and system for bit-deskewing are described. Embodiment includes a computer system with multiple components that transfer data among them. In one embodiment, a system component receives a forward strobe signal and multiple data bit signals from a transmitting component. The receiving component includes a forward strobe clock recovery circuit configurable to align a forward strobe sampling clock so as to improve sampling accuracy. The receiving component further includes at least one data bit clock recovery circuit configurable to align a data bit sampling clock so as to improve sampling accuracy, and to receive a signal from the forward strobe clock recovery circuit that causes the data bit sampling clock to track the forward strobe sampling clock during system operation.

Bit-deskewing IO method and system

A system and method for transmitting client phase information to a host device over a bidirectional data link is described. Embodiments include detecting a phase of a clock signal relative to a data signal transmitted between a host device and a client device over a bidirectional data link. The data link includes one or more data lines each configured to transmit a corresponding bit of the data signal. The phase is encoded as client phase information and transmitted between the host and client device over the one or more data lines. The client phase information is transmitted during an electrical turnaround time period of the bidirectional data link between a read and write operation over the data link.

Method and system for communicated client phase information during an idle period of a data bus

Asymmetrical IO method and system

A method for data analysis of power modeling for a microprocessor has been developed. The method takes multiple values of power data from a power modeling simulator and generates summary data to characterize the power data behavior. Summary data views include results characterizing behavior in a single cycle and behavior across multiple cycles. Data is viewed both at an absolute level to characterize total power and relative to previous levels to characterize power derivatives. Summary data is derived from power generated every cycle when running specific benchmark programs on the power simulator.

Data analysis techniques for dynamic power simulation of a CPU

Input/output data transmission between a transmitting integrated circuit and a receiving integrated circuit requires a clock domain synchronizer to synchronize incoming data aligned to a clock signal of the transmitting integrated circuit to a clock signal of the receiving integrated circuit. During a start-up routine, the clock domain synchronizer propagates a pre-determined pattern of data bits through a first circuit path designed to reduce or eliminate metastability. During a normal operations mode, the clock domain synchronizer synchronizes the data signal to the clock signal of the receiving integrated circuit through a second circuit path.

Fully stable clock domain synchronization technique for input/output data transmission

The present invention is an apparatus and method for increasing the amount of data on a transmission path on a printed circuit board. Conventional methods allow only one data signal to be transmitted on the transmission path. The present invention uses multiple transmitters to modulate multiple data signals to form multiple modulated signals. The modulated signals are transmitted, possibly simultaneously, on the transmission path to receivers configured to demodulate individual modulated signals and recover the original data signals.

Simultaneous multi-band transmission on a printed circuit board

An input/output interface is used to transmit data between a transmitting circuit and a receiving circuit. Selectively during both system startup and system operation, a known bit pattern transmitted by the transmitting circuit is compared to a received bit pattern. The received bit pattern may be seen at the receiving circuit or a voltage regulator that is used to control the power supply level of the input/output interface. Dependent on the comparison of the known bit pattern and the received bit pattern, a bit error rate across the input/output interface is determined, in response to which the voltage regulator adjusts the power supply level of the input/output interface.

Dynamic calibration of I/O power supply level

A Mobile Subscriber Directory Assistance (MSDA) system including originating carrier center initiating a directory assistance call, a directory assistance center providing a directory assistance service, and a search environment. The search environment includes an aggregated pointer database and at least one directory number resolution database. A caller requesting a telephone number is connected to a directory assistance service center where search criteria for the requested number are taken. The requested number is identified by searching the aggregated pointer database and the directory number resolution database. The caller is connected to the identified telephone number without releasing this identified telephone number.

Method and apparatus for receiver circuit tuning

A calibration and adjustment system for post-fabrication control of a delay locked loop bias-generator is provided. The calibration and adjustment system includes an adjustment circuit operatively connected to the bias-generator, where the adjustment circuit is controllable to facilitate a modification of a voltage output by the bias-generator. Such control of the voltage output by the bias-generator allows a designer to achieve a desired delay locked loop performance characteristic after the delay locked loop has been fabricated. A representative value of the amount of adjustment desired in the bias-generator output may be stored and subsequently read to adjust the delay locked loop.

Method and apparatus to store delay locked loop biasing parameters

An analog debugging block of an integrated circuit includes a multiplexor, a buffer, and a voltage-controlled oscillator. An analog voltage signal-of-interest is selectively passed through the multiplexor to the buffer. The buffer outputs an analog control voltage dependent on the selected analog voltage signal-of-interest. The analog control voltage serves as an input to the voltage-controlled oscillator and is used to control a frequency of a digital output signal generated from the voltage-controlled oscillator. The digital output signal from the voltage-controlled oscillator is driven off-chip, whereupon a frequency of the digital output signal is determined and compared against a collection of known frequencies that correspond to particular known voltages of the analog voltage signal-of-interest, thereby resulting in a determination of the value of the selected analog voltage signal-of-interest.

IC analog debugging and calibration thereof

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Fremont, CA, United States of America

Claude R Gauthier