International Business Machines Corporation

Cisco Technology, Inc.

Claude Pin

Patrick Michel

Alain Benayoun

Jean-Francois Le Pennec

Jean L Calvignac

Gilles Toubol

Bernard J Naudin

Eric Saint-Georges

Jean Francois Le Pennec

Jacques Feraud

Jean-Francois Pennec

A hardware device for concurrently processing a fixed set of predetermined tasks associated with an algorithm which includes a number of processes, some of the processes being dependent on binary decisions, includes a plurality of task units for processing data, making decisions and/or processing data and making decisions, including source task units and destination task units. A task interconnection logic means interconnect the task units for communicating actions from a source task unit to a destination task unit. Each of the task units includes a processor for executing only a particular single task of the fixed set of predetermined tasks associated with the algorithm in response to a received request action, and a status manager for handling the actions from the source task units and building the actions to be sent to the destination task units.

Hardware device for processing the tasks of an algorithm in parallel

A hardware device for processing the tasks of an algorithm of the type having a number of processes the execution of some of which depend on binary decisions has a plurality of task units (), each of which are associated with a task defined as being either one process or one decision or one process together with a following decision. A task interconnection logic block () is connected to each task unit for communicating actions from a source task unit to a destination task unit. Each task unit includes a processor () for processing the steps of the associated task when a received action requests such a processing. A status manager () handles actions coming from other task units and builds actions to be sent to other task units.

A hardware device for processing the tasks of an algorithm of the type having a number of processes the execution of some of which depend on binary decisions has a plurality of task units (), each of which are associated with a task defined as being either one process or one decision or one process together with a following decision. A task interconnection logic block () is connected to each task unit for communicating actions from a source task unit to a destination task unit. Each task unit includes a processor () for processing the steps of the associated task when a received action requests such a processing. A status manager () handles actions coming from other task units and builds actions to be sent to other task units

System for transferring a data file from a web server to a user workstation through a network and reciprocally, the user workstation including a hard disk () for storing the data file being transferred over a SCSI bus (). The user workstation includes a dual-port memory () for storing temporarily the data file, a network logic unit () interconnected between the network and the input port of the dual-port memory for receiving the data file from the network and transmitting it to the dual-port memory, and a SCSI logic unit () interconnected between the output port of the dual-port memory and the SCSI bus for transferring the data file from the dual-port memory to the hard disk over the SCSI bus and reciprocally.

System for transferring data files between a user workstation and web server

A system and method for performing interleaved packet processing. A packet includes a source address bit pattern and a destination address bit pattern that are processed by a task processor in accordance with a data tree. A first bank of registers is utilized to load an instruction to be executed by the task processor at nodes of the data tree in accordance with the source address bit pattern. A second bank of registers is utilized for loading an instruction to be executed by the task processor at nodes of the data tree in accordance with the destination address bit pattern. A task scheduler enables the first bank of registers to transfer an instruction loaded therein for processing by the task processor only during even time cycles and for enabling the second bank of registers to transfer an instruction loaded therein for processing by the task processor only during odd time cycles.

Interleaved processing system for processing frames within a network router

Hardware device for parallel processing a determined instruction of a set of instructions having a same format defining operand fields and other data fields, the execution of this determined instruction being represented as an algorithm comprising a plurality of processes, the processing of which depending on decisions. Such a device comprises means ( ) for activating the processing of one or several processes ( ) determined by the operand fields of the instruction, decision macroblocks ( ) each being associated with a specific instruction of the set of instructions, only one decision marcoblock being selected by the determined instruction in order to determine which are the process(es) to be activated for executing the determined instruction.

Hardware device for parallel processing of any instruction within a set of instructions

The present invention is directed to a hardware device for parallel processing a determined instruction of a set of programmable instructions having a same format with an operand field defining the execution steps of the instruction corresponding to the execution of micro-instructions, comprising decision blocks ( ) being each associated with a specific instruction of the set of programmable instructions, only one decision block being selected by the determined instruction in order to define which are the specific micro-instructions to be processed for executing the determined instruction, activation blocks ( ) respectively associated with the decision blocks for running one or several specific micro-instructions, only the activation block associated with said selected decision block being activated to run the specific micro-instructions, and a micro-instruction selection block ( ) connected to each activation block for selecting the specific micro-instructions to be executed.

Hardware device for executing programmable instructions based upon micro-instructions

A device for parallel processing of subtrees within a binary tree for searching for the tree leaf matching a search key. The search is performed at each node by applying a recursive function associated with each node and whose parameters depend on the node for determining which branch, left or right, is to be taken in accordance with the search key. The device includes subtree register blocks for storing the recursive functions, processors for processing the recursive functions, a control unit that assigns one processor to the processing of the recursive functions contained in a block that sent the request to the control unit, and means for selecting subtrees included in the sequence of branches between the root and the leaf defined in accordance with the search key in response to the processing of blocks.

Parallelized processing device for processing search keys based upon tree structure

The ATM bus ( ) is composed of a clock signal, CLK, a synchronization signal, -SYNC, a data bus, S( - ), and an adapter identification bus, SID( - ). It is a synchronous bus running at any clock rates. The clock signal is generated by the backplane ( ) and transmitted to each adapter ( - -N). During each clock cycle, the data bus has three serialized operation modes (or cycles) defined in this order: a bus_req cycle of 1 clock period, a bus_ack cycle of 1 clock period and an ATM cell_xfr cycle of 14 clock periods. The free-running synchronization signal is generated on the backplane ( ) and transmitted to each adapter ( - -N). The activation of the synchronization signal of one bit of the data bus, S( - ), starts the bus_req cycle. In each case, the remaining data bus signals are left in high impedance state. To increase the bus performance, the synchronization signal is held active until an adapter activates its bus_request signal. For the bus_ack cycle, an arbiter located in a control logic ( ) determines which adapter has the bus granted for its data transfer by generating an acknowledge signal to the corresponding requester during one clock period following the deactivation of the synchronization signal. The next fourteen clock periods starts the xfer_cycle for transferring one ATM cell from a requester adapter to a destination adapter. At the end of this transmission, another req_cycle starts by the activation of the synchronization signal.

Method of operating an internal high speed ATM bus inside a switching core

A method is disclosed for making a selection on a pattern sequence depending on whether or not the sequence belongs to a routing set, the routing set having at least two keys. The selection is made in a single step by analyzing a selection word (CASE SELECT) identifying the routing set.

Method for selection on a pattern sequence

A method is disclosed for comparing a pattern sequence with a variable length key. A first bit of this sequence is identified by a pointer, the length and the location of the key are identified by a code word (W, S), the method includes a preliminary step of identifying the sequence and then performing a comparison with the variable length key.

Method for comparison between a pattern sequence and a variable length key

A FISU frame handler which is connected between an adapter and a SS7 low speed network. For each FISU frames transmitted or received in the adapter, an interrupt is generated to a processor located in the adapter. In order to diminish the number of processor interruptions, the FISU frames are externally processed by the FISU frame handler by discarding repeated FISU frames transmitted from the network so as to generate idle state signals to the adapter and by converting idle state signals received from the adapter into repetitive FISU frames to transmit them to the network without interrupting the processor. In order to perform both functions, the FISU frame handler comprises two dedicated hardware units which operate according to specific methods.

Method and apparatus for processing FISU frames according to the Signalling System 7 protocol

The bit streams, transporting the frames, received from lines (6) are placed in register 12 in such a way that n bits are processed in parallel during a time interval T. Parallel processor 10 counts the consecutive logical '1' bits beginning at the low order (left most) bit of the n bits received in interval T and from the bits received in the previous interval T-1, to determine when this number is found equal to 5 which bits have to be deleted, and when this number is found equal to 6 whether a flag is received. As a result, it reassembles N-bit characters, with N&lt;n, in register (16). The frame characters to be sent on lines (6) are stored into register (28), and processed in parallel in a time interval T by processor 10 which inserts 0 after five consecutive logical '1's' as a function of the value of the N bit and as a function of the bits of the previous character, to store into register (32), the bits which are sent on lines (6).

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Nice, France

Claude Pin