Motorola Corporation

Freescale Semiconductor,inc.

Cyrix Corporation

Claude Moughanni

William C Moyer

Taimur Aslam

Mark W McDermott

Christopher K Y Chun

Yui K Ho

Elie I Haddad

Carl S Dobbs

Kenneth R Burch

Shahid Ali

Shivraj Gurpadappa Dharne

Milind P Padhye

Mitchell K Alsup

Jeffrey E Maguire

Jeff Maguire

Yung Wu

Rama K Lakamsani

Power consumption may be reduced through the use of power gating in which power is removed from circuit blocks or portions of circuit blocks in order to reduce leakage current. One embodiment uses a modified state retention flip-flop capable of retaining state when power is removed or partially removed from the circuit. Another embodiment uses a modified state retention buffer capable of retaining state when power is removed or partially removed from the circuit. The state retention flip-flop and buffer may be used to allow for state retention while still reducing leakage current. Also disclosed are various methods of reducing power and retaining state using, for example, the state retention flip-flops and buffers. For example, software, hardware, or a combination of software and hardware methods may be used to enter a deep sleep or idle mode while retaining state.

State retention within a data processing system

A level shifter for an integrated circuit. In one embodiment, the level shifter is a bi-directional level shifter with a signal terminal located in each voltage domain that can be utilized as input or output terminal. In some embodiments, the level shifter includes transistors for cutting off the flow of current between domain power supplies when the input terminals are at a particular state. In one embodiment, only one signal line of the level shifter crosses a domain boundary.

Level shifter

A method for driving a multiplexed LCD panel (38). An LCD controller (20) controls the LCD panel (38) and provides a low power mode which refreshes a subset of the display panel (40) sequentially while refreshing the rest of the panel (38) in parallel. By resolving the panel into these portions, the present invention reduces the power consumption of an LCD module. Display information is stored in a memory (12) and provided to the controller (38) which drives the LCD panel (38). A reset signal eliminates fetching and clocking of zeroes for common areas in the display. One embodiment bit fills to provide a two tone display in low power mode.

LCD driver module and method thereof

A data processor (10) flexibly interfaces with both a variety of memory devices and external peripheral devices. A control register (94) is provided for dynamically controlling an electrical interface configuration of the data processor. A set of bits (DA) in the control register (94) provides configuration control which indicates a voltage level of data communicated with the data processor.

Low power data processing system for interfacing with an external device

A method and apparatus for providing memory patching in a data process system (5). In one embodiment, access control register (32), found in protection registers (20), contains six fields corresponding to six blocks of memory within the ROM (14). Each field includes a patch protect bit (36 and 42) as well as other access protect bits such as read protect and execute protect. The access control unit (28) selectively outputs an access error to the CPU (10) based on the state of the protect bits corresponding to the block of memory being accessed. The patch protect bit, by way of a force patch exception signal (19), alerts the CPU (10) whether the corresponding block of ROM (14) requires a patch. If a patch is required, the maskable address comparator (50) defines the size of the memory patch where the size of the patch can range from a single address location to multiple lines or blocks of contiguous memory.

Data processing system with memory patching and method thereof

A data processing system (10) which detects unauthorized memory accesses has trap door logic (17) that receives memory address bus (16) signals from a processor (12). The trap door logic (12) utilizes address detection logic (50, 52) to identify page numbers utilizing high order address bits and trap regions utilizing low order address bits. The resulting page number (70-76) signals and trap region (41-44) signals are selectively combined (54) to generate an exception signal (18) which is received by security logic (19). The selective combination (54) may be programmed, or may be fixed during fabrication. In response to the exception signal (18), the security logic (19) implements a predefined security policy, which is transmitted to the processor (12) over control lines (20).

Data processing system and method which detect unauthorized memory

A data processor (20) includes a firewall circuit (50) that monitors privilege level changes or transitions between privilege modes, such as from user mode and user space into supervisory or privileged mode and operating system space. The firewall circuit starts a timer (54) whenever a central processing unit (22) enters supervisor mode. If the timer (54) determines the passage of a predetermined time while the central processing unit remains continuously in supervisory mode without re-entering user mode, a predefined security policy is invoked. For example, the security policy may require at this point that the data processor (20) is to be reset. Different timer (54) time-out values and different security policies can be set for different types of privilege level changes. In one embodiment, a default time-out value provides protection for multiple types of privilege level changes.

Data processor with a privileged state firewall and method therefore

A data processor (10) flexibly interfaces with both a variety of memory devices and external peripheral devices. A control register (94) is provided for dynamically controlling an electrical interface configuration of the data processor. A set of bits (DA) in the control register (94) provides configuration control which indicates a pair of voltage level of data communicated with the data processor.

A method and apparatus for providing access protection in an integrated circuit (10). In one embodiment access protection circuitry (11) includes access attribute bits (51) which are compared to the access attributes (68) of a memory (14) request. If a mismatch occurs, an access fault signal (52) is asserted. If access fault signal (52) is asserted and a selective reset bit (48) has selected a first memory protection mode, then signal generation circuitry (44) asserts a reset signal (58). Reset signal (58) may be used to initiate a hardware reset of data processor (10). If access fault signal (52) is asserted and a selective reset bit (48) has selected a second memory protection mode, then signal generation circuitry (44) asserts an exception occurred signal (60).

Method and apparatus for providing access protection in an integrated

A data processor (10) flexibly interfaces with both a variety of memory devices and external peripheral devices. A control register (94) is provided for dynamically controlling an electrical interface configuration of the data processor. A set of bits (DA) in the control register (94) provides configuration control which indicates a pair of voltage levels of data communicated with the data processor.

Bidirectional handshake protocol circuitry is provided for asserting and deasserting a signal across a single line between a first device and a second device. Only the first device is permitted to assert the signal on the single line; and only the second device is permitted to deassert the signal on the single line. The protocol is particularly useful between a chipset and a CPU where the chipset asserts a System Management Interrupt (SMI) and the CPU deasserts the interrupt to signal to the chipset that the service routine is complete. After assertion (or deassertion), there is an overlap or hand-off period whereby the single line is driven in the same direction by both devices. After a predetermined number of clock cycles, the device which asserted or deasserted the signal is tristated to await deassertion or assertion, respectively.

Bidirectional single-line handshake with both devices driving the line

A data processing system (20) allows a user of a pager to receive an electronic message in a language of their own choice rather than the language of a message sender. During operation, the data processing system is enabled to receive (12) an incoming message and, subsequently, detect a language of the incoming message. If the language is different than a default language of the user, the message is translated to a default language of the user (34). The message is then be displayed (40) on a screen of a paging device in the language preselected by the user or provided via a voice synthesizer (50) for an audio message. The choice of use of a visual display or use of the voice synthesizer is preselected by the user.

Language translating pager and method therefor

A scan register (80) provides for the decoupling of the scan data output signal (117) from the data output signal (116). This is provided through a tri-statable device (88), which is controlled by a scan enable signal or by the scan clock signal.

Scan register with decoupled scan routing

A latch (40) has a clocked feedback path (46) which performs a static latching function while using less power. The latch includes a feedback device (46) which is selectively decoupled from a feed-forward portion (42, 44) of the latch. In a normal mode of operation when the latch will be clocked often, the feedback device of the latch is not enabled and the latch effectively functions as a dynamic latch. When the latch becomes inactive for an extended period of time, the feedback device is again enabled and the latch is able to store a data value indefinitely.

Feedback latch and method therefor

A wireless paging device (10) is able to control an electronic device (50) at a remote location. The wireless paging device includes a receiver (12) such as those typically used in pagers to detect when a particular electronic device is being remotely accessed. If the electronic device is being remotely accessed, a data processing system (20) stores an incoming message in a buffer (24) and subsequently determines if the incoming message is a command or another type of communication (34, 36). The data processing system will process a command to provide the proper control signals for controlling the functionality of the electronic device (50).

Growing community of inventors

Austin, TX, United States of America

Claude Moughanni