International Business Machines Corporation

Nantero, Inc.

Other

Nanotero, Inc.

Nanatero, Inc.

Claude Louis Bertin

Thomas Rueckes

Brent M Segal

William R Tonti

Wayne John Howell

Erik L Hedberg

X M Henry Huang

Mitchell Meinhold

Jack Allan Mandelman

John Atkinson Fifield

Darren K Brock

Steven L Konsek

John Edward Cronin

Russell J Houghton

Ramesh Sivarajan

Kenneth E Beilstein, Jr

Howard L Kalter

Venkatachalam C Jaiprakash

Jonathan Wesley Ward

Frank Guo

Eliodor G Ghenciu

Bernhard Vogeli

Christopher P Miller

James Marc Leas

Wilbur David Pricer

Jerzy Maria Zalesinski

H Montgomery Manning

David J Perlman

C Rinn Cleavelin

Gordon A Kelley, Jr

Thomas George Ference

Nicholas Martin Van Heel

Wayne Frederick Ellis

Anthony Richard Bonaccio

Francis Roger White

Kenneth Joseph Goodnow

Lee Edward Cleveland

Mark William Kellogg

Thomas M Maffitt

Alvar Antonio Dean

Jeffrey P Gambino

Ramachandra Divakaruni

Paul A Farrar

Timothy Harrison Daubenspeck

Timothy Dooling Sullivan

Edmund Juris Sprogis

Timothy Jay Dell

Edward J Nowak

Chung H Lam

Steven H Voldman

Sebastian Theodore Ventrone

Mark Vincent Pierson

Peter Austin Burke

Donald M Kenney

Max Gerald Levy

Joseph M Mosley

Harish N Kotecha

John Eugene Berg

Steven William Tomashot

Robert G Baker

Yoshinori Sakaue

Donelli J DiMaria

Hsing-San Lee

Louis L Hsu

John Ulrich Knickerbocker

Richard Quimby Williams

Scott Whitney Gould

Fariborz Assaderaghi

Michael D Armacost

Glen Arnold Rosendale

Donald Lawrence Wheater

Richard Carter

Jeffrey H Dreibelbis

William T Chen

Verne C Hornback

Patrick Edward Perry

Dennis A Schmidt

Francisco H De La Moneda

Ronald R Troutman

Rick L Mohler

Joseph Angelo Benenati

Jai P Bansal

Colin D Yates

Gustav Schrottke

Thomas E Dinan

Toshiharu Furukawa

John J Ellis-Monaghan

Terence B Hook

Garo Jacques Derderian

Michael A Gaynes

Toshiaki Kirihata

Chandrasekhar Narayan

Anilkumar Chinuprasad Bhatt

Derryl D J Allman

Minh H Tong

William E Bernier

Bruce Joseph Whitefield

Dale E Pontius

Paul E Bakeman, Jr

Paul A Totta

The present disclosure generally relates to multi-switch storage cells (MSSCs), three-dimensional MSSC arrays, and three-dimensional MSSC memory. Multi-switch storage cells include a cell select device, multiple resistive change elements, and an intracell wiring electrically connecting the multiple resistive change elements together and to the cell select device. MSSC arrays are designed (architected) and operated to prevent inter-cell (sneak path) currents between multi-switch storage cells, which prevents stored data disturb from adjacent cells and adjacent cell data pattern sensitivity. Additionally, READ and WRITE operations may be performed on one of the multiple resistive change elements in a multi-switch storage cell without disturbing the stored data in the remaining resistive change elements. However, controlled parasitic currents may flow in the remaining resistive change elements within the cell. Isolating each multi-switch storage cell in a three-dimensional MSSC array, enables in-memory computing for applications such as data processing for machine learning and artificial intelligence.

Three dimensional (3D) memories with multiple resistive change elements per cell and corresponding architectures for in-memory computing

Three dimensional (3D) memories with multiple resistive change elements per cell and corresponding architectures

The present disclosure is directed toward carbon based diodes, carbon based resistive change memory elements, resistive change memory having resistive change memory elements and carbon based diodes, methods of making carbon based diodes, methods of making resistive change memory elements having carbon based diodes, and methods of making resistive change memory having resistive change memory elements having carbons based diodes. The carbon based diodes can be any suitable type of diode that can be formed using carbon allotropes, such as semiconducting single wall carbon nanotubes (s-SWCNT), semiconducting Buckminsterfullerenes (such as C60 Buckyballs), or semiconducting graphitic layers (layered graphene). The carbon based diodes can be pn junction diodes, Schottky diodes, other any other type of diode formed using a carbon allotrope. The carbon based diodes can be placed at any level of integration in a three dimensional (3D) electronic device such as integrated with components or wiring layers.

Electrostatic discharge protection devices using carbon-based diodes

Under one aspect, a non-volatile nanotube diode device includes first and second terminals; a semiconductor element including a cathode and an anode, and capable of forming a conductive pathway between the cathode and anode in response to electrical stimulus applied to the first conductive terminal; and a nanotube switching element including a nanotube fabric article in electrical communication with the semiconductive element, the nanotube fabric article disposed between and capable of forming a conductive pathway between the semiconductor element and the second terminal, wherein electrical stimuli on the first and second terminals causes a plurality of logic states.

Nonvolatile nanotube switch elements using sidewall contacts

Methods for reading and programming one or more resistive change elements within a 1-R resistive change element array are disclosed. These methods include using measurement and storage elements to measure the electrical response of one or more selected cells within an array and then comparing that stored electrical response to the electrical response of a reference element within the array to determine the resistive state of the one or more selected cells. These methods also include programming methods wherein selectable current limiting elements are used to permit or inhibit programming currents from flowing through selected and unselected cells, respectively. These methods further include programing methods that use specific biasing of array lines to provide sufficient programing currents through only selected cells.

Methods for accessing 1-R resistive change element arrays

A high-speed memory circuit architecture for arrays of resistive change elements is disclosed. An array of resistive change elements is organized into rows and columns, with each column serviced by a word line and each row serviced by two bit lines. Each row of resistive change elements includes a pair of reference elements and a sense amplifier. The reference elements are resistive components with electrical resistance values between the resistance corresponding to a SET condition and the resistance corresponding to a RESET condition within the resistive change elements being used in the array. A high speed READ operation is performed by discharging one of a row's bit lines through a resistive change element selected by a word line and simultaneously discharging the other of the row's bit lines through of the reference elements and comparing the rate of discharge on the two lines using the row's sense amplifier. Storage state data are transmitted to an output data bus as high speed synchronized data pulses. High speed data is received from an external synchronized data bus and stored by a PROGRAM operation within resistive change elements in a memory array configuration.

Methods for programing DDR compatible open architecture resistive change element arrays

A non-volatile nanotube switch and memory arrays constructed from these switches are disclosed. A non-volatile nanotube switch includes a conductive terminal and a nanoscopic element stack having a plurality of nanoscopic elements arranged in direct electrical contact, a first comprising a nanotube fabric and a second comprising a carbon material, a portion of the nanoscopic element stack in electrical contact with the conductive terminal. Control circuitry is provided in electrical communication with and for applying electrical stimulus to the conductive terminal and to at least a portion of the nanoscopic element stack. At least one of the nanoscopic elements is capable of switching among a plurality of electronic states in response to a corresponding electrical stimuli applied by the control circuitry to the conductive terminal and the portion of the nanoscopic element stack. For each electronic state, the nanoscopic element stack provides an electrical pathway of corresponding resistance.

Nonvolatile nanotube switches with reduced switching voltages and currents

Under one aspect, a covered nanotube switch includes: (a) a nanotube element including an unaligned plurality of nanotubes, the nanotube element having a top surface, a bottom surface, and side surfaces; (b) first and second terminals in contact with the nanotube element, wherein the first terminal is disposed on and substantially covers the entire top surface of the nanotube element, and wherein the second terminal contacts at least a portion of the bottom surface of the nanotube element; and (c) control circuitry capable of applying electrical stimulus to the first and second terminals. The nanotube element can switch between a plurality of electronic states in response to a corresponding plurality of electrical stimuli applied by the control circuitry to the first and second terminals. For each different electronic state, the nanotube element provides an electrical pathway of different resistance between the first and second terminals.

Nonvolatile nanotube memory arrays using nonvolatile nanotube blocks and cell selection transistors

Resistive change element arrays using a reference line

Methods for scaling dimensions of resistive change elements, resistive change element arrays of scalable resistive change elements, and sealed resistive change elements are disclosed. According to some aspects of the present disclosure the methods for scaling dimensions of resistive change elements and the resistive change element arrays of scalable resistive change elements reduce the impact of overlapping materials on the switching characteristics of resistive change elements. According to some aspects of the present disclosure the methods for scaling dimensions of resistive change elements include sealing surfaces of resistive change elements. According to some aspects of the present disclosure the methods for scaling dimensions of resistive change elements include forming barriers to copper migration in a copper back end of the line.

Methods of making sealed resistive change elements

Inverter circuits and NAND circuits comprising nanotube based FETs and methods of making the same are described. Such circuits can be fabricating using field effect transistors comprising a source, a drain, a channel region, and a gate, wherein the first channel region includes a fabric of semiconducting nanotubes of a given conductivity type. Such FETs can be arranged to provide inverter circuits in either two-dimension or three-dimensional (stacked) layouts. Design equations based upon consideration of the electrical characteristics of the nanotubes are described which permit optimization of circuit design layout based upon constants that are indicative of the current carrying capacity of the nanotube fabrics of different FETs.

Logic elements comprising carbon nanotube field effect transistor (CNTFET) devices and methods of making same

Non-linear resistive change memory cells and arrays

Double density nonvolatile nanotube switch memory cells

Method for programming 1-R resistive change element arrays

Methods for forming crosspoint arrays of resistive change memory cells

Growing community of inventors

Venice, FL, United States of America

Claude Louis Bertin