Sgs-thomson Microelectronics S.a.

Thomson-csf

Thomson-csf Telephone

Le Materiel Telephonique Thomson-csf

Societe Des Telephones Ste (thomson-ericsson)

Claude Athenes

Pierre Charransol

Jacques Hauri

Jacques E Salle

Bernard Louis-Gavet

Jean-Claude Audrix

Francois Tarbouriech

Pascal Moniot

Jean Pierre Landez

Jean-Louis Bernet

Philippe Blouin

Jean-Bernard Saxod

Jean L Meresse

Jean-Claude Longchambon

Gerard Poux

Jean C Audrix

This invention relates to a device for organizing access to a bus connecting a memory to at least two entities asynchronous binary signals representing requests for access to the bus. The device supplies binary signals to authorize the access to an entity based on a priority determination between the different requests and includes a priority decoder in wired logic associated with an input register. A loading of the state of the access request signals happens, if an access request is present while a read or write cycle of the memory is executed, upon the arrival of a pulse on a signal issued by a memory controller associated with the memory and indicative of the end of a memory cycle.

Device for organizing the access to a memory bus

This device controls the interrupts of a microprocessor based on events occurring in at least one entity associated with this microprocessor. The device organizes the storage of words representative of at least an origin and a type of the interrupt issued by the entity. The interrupts from the entity are stored in an area of a memory. When there is more than one entity, each entity has an area of memory allocated to it. The microprocessor can access these memory areas and process the interrupts. An indicator is also provided so that the device can tell when a memory area has become full.

Apparatus for postponing processing of interrupts by a microprocessor

This invention relates to a device for organizing access to a bus connecting a memory to at least two entities issuing asynchronous binary signals representing requests for access to the bus. The device supplies binary signals to authorize the access to an entity based on a priority determination between the different requests and includes a priority decoder in wired logic associated with an input register. A loading of the state of the access request signals happens, if an access request is present while a read or write cycle of the memory is executed, upon the arrival of a pulse on a signal issued by a memory controller associated with the memory and indicative of the end of a memory cycle.

This invention relates to a matrix for switching between two time-division multiplex groups, including three areas for buffering the data arriving in multiplex onto input junctions, which issue these data in multiplex to output junctions according to an assignment of each time slot of an input multiplex to a time slot of an output multiplex, a first area being meant for receiving the data relative to the transmissions as they are issued by a series-to-parallel converter receiving the input junctions and for enabling, at least when the data belong to a transmission channel including several time slots of a same multiplex, a transfer of the data to one of the two other buffer areas according to the parity of the multiplex frame it contains.

Matrix for switching between two multiplex groups

A device for transferring binary data between a time-division multiplex and a RAM includes circuitry for assigning, for each time slot of the multiplex, a logical channel number. This enables two HDLC controllers, respectively for transmission and reception, to be shared between all the channels of the multiplex.

Device for binary data transfer between a time-division multiplex and a

This invention relates to an integrated HDLC circuit of the type including at least one HDLC controller and one DMA controller, and means for organizing the access to a first external bus for connection to an external memory, via an internal bus to which are connected different entities, which require to have access to the external memory, the internal bus being connected to the first external bus via a memory controller integrated in the HDLC circuit.

HDLC integrated circuit using internal arbitration to prioritize access

A process for converting a first flow of data words supplied at the rate of a first clock into a second flow of data words comprising, inside the successive frames, a sequence of n data words of the first flow and accompanying data, the duration of each frame of the second flow being equal to the duration of n data words in the first flow. Said process comprises: storing the successive data words of the first flow in an input register (1); as soon as the register is full, writing its content in one of p intermediate registers (A, B, C); sequentially reading the p intermediate registers in an output register (5); and if, during a frame, the writing and reading sequence in the intermediate registers is such that an intermediate register is read while its writing has not been modified, skipping, at the beginning of the following frame, one reading order until one obtains an adequate synchronization which will then be maintained during the subsequent frames.

Transceiving process for a digital telephone line

A prediffused integrated circuit having rows of basic cells on a substrate. Each basic cell includes two MOS transistors connected in series through a common drain or source electrode, each transistor having a separate gate. All basic cells in a row are the same type while adjacent rows alternate between p-type and n-type.

Prediffused integrated circuit and a method of interconnection of the

A logic selection module for forming the interface between the two central units and eight selection circuits of an electronic time automatic telephone switchboard and which comprises means for selecting the calling central unit, means for connecting the thus selected central unit, means for decoding the address of one of the eight selection circuits to which the module is connected in the signal received from the thus selected central unit and means for transmitting the marking signals received from the central unit to the said circuit, whose address has been decoded.

Logic selection module

The system is constituted by a wired logic included in a signalling unit, which also has a microcomputer. This logic is connected on the one hand to the incoming and outgoing signalling junctions of a connection network and on the other to a programmed peripheral marking unit by means of which a central computer supplies correspondence data between an incoming junction channel and an outgoing junction channel.

Signalling switching system in a time switching network and time

A clock recovery device for a digital data receiver. This device includes a first register for generating a clock signal having the same nominal frequency as the distant clock signal; a second register for detecting the pulses of the received signals, regenerating these received signals and then generating synchronization pulses, and a third register for retiming the regenerated pulses.

Clock recovery device

The modular switching network for time-division telephone exchanges, which may be applied to small-capacity time-division telephone exchanges, is constituted by the direct connection of pairs of subscriber and trunk line connecting units by PCM digital trunks, each connecting unit comprising a concentration-deconcentrator device for serving the subscribers associated with this connecting unit.

Modular time-division switching network

A switching system for telephone exchanges employing pulse code modulation (PCM). The time division switching network uses standard circuits of a single type, i.e., symmetrical time division matrices (MTS) and, in a particular embodiment, one PCM telephone junction is multipled onto two inputs of two MTSs and the latter are rejoined by two bi-directional junctions so that the construction of telephone exchange according to the invention permits simple and easy extensions of the capacity of the switching system.

Time division switching network

A switching network with k=p+q inputs and as many outputs comprises one or more symmetrical time-division matrices, k being eight or a multiple of eight in the embodiments specifically disclosed. A larger number p of incoming subscriber links and a smaller number q of exchange outputs are respectively connected to p outgoing subscriber links and q exchange inputs. Digitized voice samples arriving over each incoming link in successive time slots of a recurrent frame, allocated to respective subscribers, are stored in each matrix and are selectively distributed to the reduced number of time slots sent to the exchange under the control of switching instructions from the exchange; conversely, signal samples received from the exchange in successive time slots are distributed to selected time slots of outgoing links. Signal paths can also be established between network inputs and outputs connected to incoming and outgoing links, thereby enabling direct communication between subscribers served by the network.

Switching network for establishing two-way connections between selected

The invention relates to the connection networks used for switching digital signals, more especially telephonic PCM signals. It consists in organizing the spatial stage of a network of the TST type operating in series mode so as to divide into two the number of switching planes of that network. Each plane is with blocking although the assembly is without blocking. Moreover the number of time paths that enables the spatial stage to be traversed is doubled.

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Paris, France

Claude Athenes