Dallas Semiconductor Corporation

Texas Instruments Corporation

Other

Clark R Williams

William J Podkowa

Ching-Lin Jiang

Michael L Bolan

Karl H Renner

Kevin E Deierling

Bradley M Harrington

Ronald W Pearson

Louis Rodriguez

Robert H Schnurr

A low power timekeeping system utilizes a state machine to first read seconds stored in a RAM and update seconds and then determine if the minutes requires updating. If the minutes do not require updating then the sequencer stops operation until the next update cycle. Similarly, the minutes, hours, days of the week, date of the month, month, and year are updated only as needed in each update cycle thereby lowering the power requirement needed by the timekeeping system.

System and method for keeping time

A dual storage cell memory includes an array of dual storage cells, each of the dual storage cells containing a first memory cell and a second memory cell. The first and second memory cells are well known six-transistor static memory cells with the addition of transfer circuitry for transferring data directly from the internal data nodes of each of the memory cells to its corresponding complementary memory cell without requiring the use of the enable transistors or the bit lines associated with each of the dual storage cells.

Dual storage cell memory

Low power timekeeping system

An integrated circuit, in which some areas of the chip are powered from battery, but at least two other areas of the chip can draw power from independent on-chip power-storage capacitors (which are diode-isolated to accumulate charge from an external signal line). The signal line's input buffer draws power from one capacitor, and the decoder logic draws power from another. Thus, even if the first capacitor is depleted by the signal line's staying in the high-current regime, it will be powered up again when the signal line is again driven high; and the charge stored in the second capacitor will permit the decoding logic to operate. Preferably the second capacitor also powers circuitry which encodes a unique serial number for the chip. Thus, even after the battery has died, the chip can be interrogated to ascertain its unique serial number.

Electronic module energy storage circuitry

An integrated circuit which includes not only a real time clock, but also an elapsed time counter, and a third counter. The elapsed time counter measures the total number of seconds during which a system has been powered up. The third counter is a 'cycle counter,' which measures the number of times a power cycle (power-up and power-down) has occurred. Thus, by reading the cycle counter and the elapsed time indicator, the general power history of a system can readily be determined, even if the system itself has totally failed. This integrated circuit is battery backed, and is advantageously combined with a system for which power history must be maintained.

Integrated circuit with real time, elapsed time, and cycle counter clocks

A timekeeping integrated circuit with devices partitioned into areas with different power supplies and level translators between the areas; the level translators use a memory cell for isolation and to shorten the signal active time for low power consumption. Also a one-wire communication port with low power input buffers may be used to detect very slowly varying voltages. The input buffers include staged decreasing resistors as a power dissipation limitation.

Low power module

Dual port static RAM with bidirectional shift capability

Integrated circuit with both battery-powered and signal-line-powered

A dynamic PLA timing circuit in a PLA ROM includes a PLA line and the address section only of another PLA line. The address section of the first PLA line is connected to the true address lines and the address section of the other PLA line is connected to the complementary address lines. Shorting bars connecting the two PLA lines are formed around each pair of true and complementary address lines such that a conductive path is formed through the address sections for any address into the ROM. The data section is connected to the gates of every data transistor. However, the drains of all but one of the data transistors are not connected to their associated data line. The data line that is connected to the associated data transistor forms the output terminal of the timing circuit.

Dynamic PLA time circuit

Arbitration logic is provided to receive conflicts between a timekeeping system and a user system which share a common memory. The common memory is comprised of an array of dual memory cells, each of which has a timekeeping cell and a user cell and circuitry for transferring data from the timekeeping cell to the user cell or from the user cell to the timekeeping cell. User data is written into the user cells when it is available and immediately thereafter is transferred from the user cells to the timekeeping cells. Data from the timekeeping system is inhibited from being written into the timekeeping cells if, during the present update cycle of the timekeeping system, the user writes data into the common memory.

Memory arbitration between timekeeping circuitry and general purpose

An integrated circuit timekeeper, which uses a hybrid hardware/software architecture, wherein the least significant bits are updated in hardware and the more significant bits are updated in software. This hybrid architecture provides improved power efficiency, layout efficiency, and flexibility in reconfiguration.

Low-power clock/calendar architecture

A low-power crystal-controlled CMOS oscillator wherein a long and wide additional transistor is provided in the first stage of the output amplifier. This prevents the output amplifier from diverting too much current from the primary amplifier stage during startup.

Low voltage oscillator with separate startup mode

A low-power crystal-controlled CMOS oscillator wherein a long and wide additional transistor is provided in the first stage of the output amplifier. This prevents the output amplifier from diverting too much current from the primary amplifier stage during start-up.

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Plano, TX, United States of America

Clark R Williams