International Business Machines Corporation

Clark M O'Niell

Jonathan James DeMent

Jason Nathaniel Dale

Steven Leonard Roberts

Christopher John Spandikow

Joseph Anthony Perrie, Iii

One of the processors of a multiprocessor system is chosen to be a boot processor. The other processors of the multiprocessor system execute masking code that generates electromagnetic and/or thermal signatures that mask the electromagnetic and/or thermal signatures of the actual boot processor. Such masking may involve running the same boot code as the boot processor but without obtaining access to security information, such as the security key for accessing the system. The electromagnetic and/or thermal signatures generated by the execution of the masking code preferably approximate the electromagnetic and/or thermal signatures of the actual boot code executing on the boot processor. In this way, it is difficult to distinguish which processor is the actual boot processor.

Masking a hardware boot sequence

Boot code is partitioned into a plurality of boot code partitions. Processors of a multiprocessor system are selected to be boot processors and are each provided with a boot code partition to execute in a predetermined boot code sequence. Each processor executes its boot code partition in accordance with the boot code sequence and signals to a next processor the successful and uncompromised execution of its boot code partition. If any of the processors does not signal successful completion and/or uncompromised execution of its boot code partition, the boot operation fails. The processors may be arranged, with regard to the boot operation, in a daisy chain, ring, or master/slave arrangement, for example.

Secure boot across a plurality of processors

Pervasive logic is provided that includes a random event generator. The random event generator randomly selects which processor of a plurality of processors in the multiprocessor system is to be a boot processor for the multiprocessor system. A corresponding configuration bit for the randomly selected processor is set to identify the processor as a boot processor. Based on the setting of the configuration bits for each processor in the plurality of processors, a selection of a security key is made. The security key is then used to decrypt the boot code for booting the multiprocessor system. Only the randomly selected boot processor is able to select the correct security key for correctly decrypting the boot code, which it then executes to bring the system to an operational state.

Selecting a random processor to boot on a multiprocessor system

A mechanism is provided for booting a multiprocessor device based on selection of encryption keys to be provided to the processors. With the mechanism, a security key and one or more randomly generated key values are provided to a selector mechanism of each processor of the multiprocessor device. A random selection mechanism is provided in pervasive logic that randomly selects one of the processors to be a boot processor and thereby, provides a select signal to the selector of the boot processor such that the boot processor selects the security key. All other processors select one of the one or more randomly generated key values. As a result, only the randomly selected boot processor is able to use the proper security key to decrypt the boot code for execution.

Booting a multiprocessor device based on selection of encryption keys to be provided to processors

Masking a boot sequence by providing a dummy processor is provided. One of the processors of a multiprocessor system is chosen to be a boot processor. The other processors of the multiprocessor system execute masking code that generates electromagnetic and/or thermal signatures that mask the electromagnetic and/or thermal signatures of the actual boot processor. The execution of the masking code on the non-boot processors preferably generates electromagnetic and/or thermal signatures that approximate the signatures of the actual boot code execution on the boot processor. One of the non-boot processors is selected to execute masking code that is different from the other masking code sequence to thereby generate an electromagnetic and/or thermal signature that appears to be unique from an external monitoring perspective.

Masking a boot sequence by providing a dummy processor

A mechanism is provided for masking a boot sequence by providing a dummy processor. With the mechanism, one of the processors of a multiprocessor system is chosen to be a boot processor. The other processors of the multiprocessor system execute masking code that generates electromagnetic and/or thermal signatures that mask the electromagnetic and/or thermal signatures of the actual boot processor. The execution of the masking code on the non-boot processors preferably generates electromagnetic and/or thermal signatures that approximate the signatures of the actual boot code execution on the boot processor. One of the non-boot processors is selected to execute masking code that is different from the other masking code sequence to thereby generate a electromagnetic and/or thermal signature that appears to be unique from an external monitoring perspective.

A cache replacement system for extending the debugging capabilities of accelerated simulation by enabling enhanced cache data and state checking is provided. The system includes a Cell Broadband Engine Architecture (CBEA) compliant system implementing Replacement Management Tables in an accelerated simulation environment. The RMTs control cache replacement and allow the software to direct entries with specific address ranges at a particular subset of the cache. The RMTs further allow for locking data in the cache and are utilized to prevent overwriting data in the cache by directing data that is known to be used only once at a particular set. Using the locking mechanism in an accelerated simulation environment, a user is able to run code sets, which, when the microprocessor system being tested is correctly designed, generates identical and verifiable data and cache states in each of the different sets of the cache.

Accelerated simulation and verification of a system under test (SUT) using cache and replacement management tables

A system and method for masking a hardware boot sequence are provided. With the system and method, one of the processors of a multiprocessor system is chosen to be a boot processor. The other processors of the multiprocessor system execute masking code that generates electromagnetic and/or thermal signatures that mask the electromagnetic and/or thermal signatures of the actual boot processor. Such masking may involve running the same boot code as the boot processor but without obtaining access to security information, such as the security key for accessing the system. The electromagnetic and/or thermal signatures generated by the execution of the masking code preferably approximate the electromagnetic and/or thermal signatures of the actual boot code executing on the boot processor. In this way, it is difficult to distinguish which processor is the actual boot processor.

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White Plains, NY, United States of America

Clark M O'Niell