Advanced Micro Devices Corporation

Clark L Buxton

Keith G Hawkins

David W Smith

Joseph A Bailey

Norman M Hack

Garth D Hillman

Donald G Craycraft

Gary Baum

A computing device has a plurality of subsystems located in subsections that are moveable with respect to each other. Communication between the subsections is accomplished with wireless transceivers transmitting over the air gap interface separating the subsections. Data from multiple communicating subsystems in the subsections is multiplexed into a single data stream and encoded into the communication protocol of the wireless transceivers. The encoded data stream is transmitted to a compatible transceiver where it is decoded. The decoded data stream is demultiplexed into individual data streams for each of the communicating subsystems. The wireless transceivers include multiple communication protocols and transmission frequencies from radio frequencies to optical frequencies. Optical fibers, transmission lines or waveguides may be used to transmit signals within each subsection depending on the wireless technology and protocol.

Wireless interface

A method and apparatus for manipulating work queue elements via a hardware adapter and a software driver. The software driver is configured to cause a plurality of work queue elements to be stored in a queue pair including a plurality of storage locations. Each of the plurality of storage locations includes an indicator indicating whether a corresponding work queue element has been completed. The hardware adapter is configured to select one of the plurality of storage locations and to service a corresponding one of the plurality of work queue elements, and in response to completion of a task associated with the corresponding work queue element, to cause the indicator to indicate that the corresponding work queue element has been completed. Additionally, the software driver is configured to cause a new work queue element to be stored in the selected storage location in response to detecting that the indicator indicates that the corresponding work queue element has been completed.

Manipulating work queue elements via a hardware adapter and software driver

An integrated processor is fabricated on a single monolithic circuit and employs circuitry to accommodate data-intensive, view-intensive and voice-intensive requirements of modern-day PIDs. The integrated processor includes a CPU core, a memory controller, and a variety of peripheral devices to achieve versatility and high performance functionality. The integrated processor consumes less power by provision of a clock control unit including a plurality of phase-locked loops for generating clock signals of differing frequencies to appropriately clock the various subsystems of the integrated processor. The clock signals provided to the various subsystems by the clock control unit are derived from a single crystal oscillator input signal. A power management unit is incorporated within the integrated processor to control the frequency and/or application of certain clock signals to the various subsystems, as well as to control other power management related functions. The pin-count of the integrated processor is finally minimized by allowing the selective multiplexing of certain external pins depending upon the desired functionality of the integrated processor.

Integrated processor system adapted for portable personal information

A computer system is presented which includes an output driver circuit with a drive strength that varies depending upon the speed of a peripheral device being accessed, the frequency of a system clock signal, and/or the system configuration. Reducing drive strength when a slow peripheral device is being accessed, the frequency of the system clock signal is reduced, or bus loading is low reduces the occurrence of large switching transients and accompanying ground bounce, power supply droop, and radiated EMI. A power management unit produces a clock frequency control signal which controls the frequency of the system clock. In one embodiment, the output driver circuit includes an address storage unit, an address comparator unit, a bus loading storage unit, a control unit, and one or more adjustable drive circuits having an output terminal coupled to a signal line of a peripheral bus. The address storage unit stores address range information associated with one or more peripheral devices coupled to the peripheral bus. The address comparator unit produces an address match signal if an address signal is within a range of addresses identified by address range information stored in the address storage unit. The bus loading unit stores peripheral bus loading information. The control unit produces one or more control signal dependent upon the address match signal, the clock frequency control signal, and/or bus loading information. Each adjustable drive circuit drives the output terminal with a drive strength determined by the one or more control signals.

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Austin, TX, United States of America

Clark L Buxton