Honeywell G.m.b.h.

Honeywell International Inc.

Clarence S Smith

Larry James Yount

Richard F Hess

Robert D Girts

Rick H Hay

A memory system for a digital computer includes a non-volatile random access memory for storing past and present values of state variables is immune from electromagnetic transients and other disturbances which can affect the integrity of the memory. Each memory cell is designed with an energy storage device and logic devices which control the logic sequence for charging of the energy storing devices. These memory cells are aligned in an array and specially designed system is included with this that takes into account the length of time required in order to charge each cell in the array.

Memory with high integrity memory cells

A flight critical computer system for an aircraft includes dual independent lanes having two processors in each lane. The first lane has a primary processor and a redundant processor and provides a first command signal. The second lane includes a primary processor and a redundant processor and provides a second command signal. A first monitor compares the primary processor of the first lane with the primary processor of the second lane and generates first comparison signals as a function of disagreement therebetween. A second monitor compares the output signals of the redundant processor of the second lane and the primary processor of the first lane and generates second comparison signals as a function of disagreement therebetween. A third monitor compares the primary processor of the second lane with the redundant processor of the first lane and generates third comparison signals as a function of disagreement therebetween. Selection logic selects as a function of the first, second and third comparison signals at least output generated by the processors as a command signal of the system while allowing for at least one processor to fail before both command signals from the lanes, respectively, are disabled.

Fail-operational fault tolerant flight critical computer architecture

An improved distributed processing system for controlling the transfer of data between a terminal controller and a subsystem is described where the improvement insures wordstring consistency in a manner which is completely transparent to the subscriber subsystem. In particular, data is transferred, via a dual-bank, dual-port terminal memory where the bank selection is controlled such that any wordstring transfers between the terminal memory and the terminal controller are constrained to involve a different bank than transfers between the terminal memory and its associated subscriber subsystem. A wordstring log associated with control arbitration logic contains the dynamic state of the bank assignments for each wordstring. Two flag bits in the wordstring log provide information to the control/arbitration logic, allowing it to manage the bank selection of the terminal memory.

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Glendale, AZ, United States of America

Clarence S Smith