International Business Machines Corporation

Globalfoundries Inc.

Clarence Rosser Ogilvie

Sebastian Theodore Ventrone

Kenneth Joseph Goodnow

David W Milton

Keith Robert Williams

Charles S Woodruff

Robert Dov Herzl

Kerry Bernstein

Tad Jeffrey Wilder

Paul Mark Schanely

Christopher B Reynolds

Christopher Douglas Hanudel

Jack Robert Smith

Robert Spencer Horton

Kenneth Anthony Lauricella

Margaret R Charlebois

Paul C Stabler

Nitin Sharma

Charles B Winn

Wilbur David Pricer

Robert Allen Drehmel

Eric Oliver Mejdrich

Giora Biran

Jamie Randall Kuesel

Bruce G Hazelzet

Mark William Kuemerle

John Sargis, Jr

Ming-i Mark Lin

Mark E Kautzman

Malede Wondmagegne Berhanu

Gordon Taylor Davis

Timothy Jay Dell

Mark William Kellogg

Michel S Michail

Roland A Bechade

Llewellyn Bradley Marshall, Iv

Richard N Wilson

Rashmi D Chatty

Seetharam Gundurao

Nishant Sharma

Matthew P Szafir

David James Hathaway

Adam James Muff

David Arnold Luick

Bartholomew Blaner

Eric A Foreman

Vladimir P Zolotov

Peter Anton Habitz

Mark Owen Maxson

Jeanne P Bickford

Jeffrey G Hemmett

Paul Steven Zuchowski

Steven Frederick Oakland

Christopher P Miller

Peter Anthony Sandon

David S Wolpert

Todd Edwin Leonard

James Anthony Marcella

Robert J Devins

Gregory John Mann

Serafino Bueti

Jason Michael Norman

Douglas P Nadeau

Arnold S Tran

Jason Edward Rotella

Stephen B Barrett

W Riyon Harding

Randall Rogers Pratt

Henry Harvey Burkhart

Scott W Rixner

William C Pearson

William K Hoffman

Matthew Adam Cushing

Allen James Gavin

Embodiments of the invention provide a method, system, and program product for predicting a delay of a critical path. In one embodiment, the invention provides a method of predicting a delay of at least one critical path of an integrated circuit, the method comprising: determining a delay of at least one ring oscillator on the integrated circuit; and calculating a predicted delay for the at least one critical path delay based on a delay of components of the critical path at a corner condition, a wire delay of the at least one critical path, a delay of the at least one ring oscillator at a corner condition, and the determined delay of the at least one ring oscillator.

Critical path delay prediction

Disclosed are a chip performance monitoring system, method and a computer program product, wherein a performance monitor output signal is propagated through an adjacent scan chain to avoid signal degradation incident to across-chip transmission of high frequency signals. Since the clock signal frequency used to control signal propagation through the scan chain will typically be less than twice the performance monitor output signal frequency, frequency sub-sampling with aliasing occurs. To compensate, signal propagation through the scan chain can be controlled during different time periods using different clock signals having different clock signal frequencies and, during these different time periods, different data outputs can be captured at an output node of the scan chain. The data output frequencies of these different data outputs can be measured and the performance monitor output signal frequency can be determined based on the different data output frequencies given the different clock signal frequencies.

Chip performance monitoring system and method

A structure and method of using the structure. The structure including an integrated circuit chip having a set of micro-channels; an electro-rheological coolant fluid filling the micro-channels; first and second parallel channel electrodes on opposite sides of at least one micro-channel, the first channel electrode connected to an output of an auto-compensating temperature control circuit, the second channel electrode connected to ground; the auto-compensating temperature control circuit comprising a temperature stable current source connected between a positive voltage rail and the output and having a temperature sensitive circuit connected between ground and the output, a leakage current of the temperature stable current source being essentially insensitive to temperature and a leakage current of the temperature sensitive circuit increasing with temperature.

Auto-compensating temperature valve controller for electro-rheological fluid micro-channel cooled integrated circuit

A reactive metal optical security device for implementation in an optical network and/or system to provide a mechanism for disrupting the optical network and/or system. The security device includes a mirror comprising a reactive metal stack and configured to reflect an optical signal and receive an electrical signal. The security device further includes a semiconductor chip configured to send the electrical signal to the mirror.

Reactive metal optical security device and methods of fabrication and use

Aspects of the invention provide for a flexible performance screen ring oscillator (PSRO) integrated within a scan chain. In one embodiment, a circuit structure to create the flexible PSRO includes: a plurality of programmable scan chain elements; and a forward test scan chain path through the plurality of scan chain elements; wherein each of the programmable scan chain elements includes additional circuitry for a backward path, such that the backward path and the forward test scan chain path are combined to create the PSRO.

Flexible performance screen ring oscillator within a scan chain

A plurality of digital circuits are manufactured from an identical circuit design. A power controller is operatively connected to the digital circuits, and a non-transitory storage medium is operatively connected to the power controller. The digital circuits are classified into different voltage bins, and each of the voltage bins has a current leakage limit. Each of the digital circuits has been previously tested to operate within a corresponding current leakage limit of a corresponding voltage bin into which each of the digital circuits has been classified. The non-transitory storage medium stores boundaries of the voltage bins as speed-binning test data. The power controller controls power-supply signals applied differently for each of the digital circuits based on which bin each of the digital circuit has been classified and the speed-binning test data.

Adaptive power control using timing canonicals

A performance screen ring oscillator (PSRO) formed from paired scan chains is disclosed. A circuit structure comprises scan chains each having scan chain elements. A scan chain link is configured to pair at least one scan chain element from a first scan chain with at least one scan chain element of a second scan chain to form a PSRO. A forward path associated with data flow through the at least one scan chain element of the first scan chain becomes a backward path of the at least one scan chain element of the second scan chain, and a forward path associated with data flow through the at least one scan chain element of the second scan chain becomes a backward path of the at least one scan chain element of the first scan chain.

Performance screen ring oscillator formed from paired scan chains

A performance screen ring oscillator (PSRO) is formed from multi-dimensional pairings of scan chains. In one embodiment, there is a multi-dimensional arrangement of scan chains in an integrated circuit. Each of the scan chains has interconnected scan chain elements that form a shift register to apply test patterns to inputs of combinational logic in the integrated circuit and read outputs from the combinational logic based on the inputted test patterns. A scan chain link links selected scan chain elements from the scan chains to form at least one PSRO loop within the multi-dimensional arrangement of the scan chains.

Performance screen ring oscillator formed from multi-dimensional pairings of scan chains

An integrated circuit chip having micro-channels formed in multiple regions of the integrated circuit chip and a method of cooling the integrated circuit chip. The method includes for any region of the multiple regions, allowing a coolant to flow through micro-channels of the region only when a temperature of the region exceed a first specified temperature and blocking the coolant from flowing through the micro-channels of the region when a temperature of the region is below a second specified temperature.

Electro-rheological micro-channel anisotropic cooled integrated circuits and methods thereof

Aspects of the invention provide a circuit structure that automatically monitors a plurality of ring oscillators and dynamically selects the fastest or the slowest ring oscillator for feedback into the plurality of ring oscillators. In one embodiment, a circuit includes: a plurality of delay elements, each delay element associated with a ring oscillator; a first logic gate for receiving outputs of each of the delay elements; a second logic gate for receiving outputs of each of the delay elements; and a multiplexer for receiving an output of the first logic gate and an output of the second logic gate and choosing one of the outputs, wherein a selection for the multiplexer is based on an output of the multiplexer. To select the fastest ring oscillator, a second multiplexer is provided.

Ring oscillator

Localized logic regions of a circuit include a local comparator electrically connected to a local resistive voltage circuit, to a local resistive ground circuit, and to a local register structure. The local comparator supplies a clock pulse to the local register structures when the local reference voltage is below a local voltage threshold. Activity in the local combinatorial logic structure causes the local reference voltage to drop below the local reference voltage independently of changes in the global reference voltage causing the comparator to output the clock pulse (with sufficient delay to allow the logic results to be stored in the registers only after setup times have been met in the local logic devices). This eliminates the need for a clock distribution tree, thereby saving power when there is no activity in the local combinatorial logic structure.

Inactivity triggered self clocking logic family

A method for designing an integrated circuit. A computer determines, for one or more paths in a circuit design, for a value of a design variable at which timing closure of the circuit design is achieved, an approximate slope of a function representing path delay as a function of the design variable. When the computer determines that one of the approximate slopes is not within a defined slope range, the computer determines an adjustment direction and an adjustment value based in part on the magnitude by which the slope is not within the defined slope range. The computer changes the circuit design of the path associated with the out-of-range slope, based in part on the adjustment direction and the adjustment value, so as to bring the slope within the defined slope range.

Circuit design using design variable function slope sensitivity

A design structure including universal peripheral processor architecture on an integrated circuit (IC) includes a first data bus and a second data bus communicating with first and second ternary content addressable memory (TCAM) devices configured as state machines. First and second processors are coupled to the first bus interface logic and the second bus interface logic. First and second data storage devices communicate with the first and second processors and are coupled to the first and second data buses and communicate with each other. The TCAM devices are configured as state machines and are coupled to and adapted to interface with the processors, the data storage devices, and the bus interface logic using predefined protocols.

Structure for hardware assisted bus state transition circuit using content addressable memories

Growing community of inventors

Huntington, VT, United States of America

Clarence Rosser Ogilvie