Motorola Solutions, Inc.

Freescale Semiconductor,inc.

Compaq Information Technologies Group, L.p.

Clarence Coffee

Melanie King

Friedrich J Bollmann

Divya Ramamoorthy

David Weygandt

Robert A Lester

Charles R Ruelke

Gary J Piccirillo

Phillip M Jones

Michael J Collins

Jerome J Johnson

Kenneth T Chin

Eytan Hartung

Wireless communication device and methods for operating the same. One wireless communication device includes an electronic processor configured to operate the wireless communication device in a first security mode of a plurality of available security modes. The electronic processor is also configured to evaluate one or more environmental context parameters associated with the wireless communication device, determine, based on the environmental context parameters, whether communications of the wireless communication device are susceptible to a potential cyber-security threat, and, in response to determining the communications of the wireless communication device are susceptible to the potential cyber-security threat, transition the wireless communication device to a second security mode of the plurality of available security modes to determine whether the potential cyber-security threat is present, wherein at least one selected from a group consisting of the frequency scanning feature and the frequency hopping feature is enabled in the second security mode.

Dynamically enabling a security feature of a wireless communication device based on environmental context

A communication system and method are provided for authenticating a portable radio from a plurality of shared portable radios. The authentication controls access to user personal profiles and public safety service applications associated with a public safety agency. A firearm having a firearm user ID stored therein, communicates the firearm user ID over short range communications to the portable radio. The firearm user ID may be used for single factor authentication or combined with a PIN entry for multi-factor authentication.

Communication system and method for controlling access to portable radio public safety service applications

Disclosed herein are multi-mode methods and devices for sample generation. An exemplary device for generating an output sample includes an analog-to-digital converter (ADC) for sampling a plurality of input analog signals and producing an ADC output sample. The ADC may include a ADC digital modulator including timing-critical components. A plurality of digital blocks may be coupled to the ADC digital modulator. The exemplary device may include a baseband processor for controlling a plurality of clock inputs. The plurality of clock inputs may drive the ADC digital modulator and the plurality of digital blocks. The baseband processor may be configured to operate in a plurality of modes including a first mode and a second mode. The first mode may include a first mode standby state and a first mode initial operating state. The second mode may include a second mode initial operating state and a second mode standby state.

Devices and methods for multi-mode sample generation

A system-on-chip () includes a 16-bit DSP (), a 16-bit data bus () coupled to the DSP, at least one 32-bit-only peripheral (), a 32-bit data bus () coupled to the peripheral, and a bridge (), including a write merge system (), coupled between the 16-bit and 32-bit buses. A method of the write merge system includes pre-storing addresses of peripherals in a memory map structure (and), receiving 16-bit data and a write transaction from the DSP for modifying sixteen bits of a 32-bit data location of the peripheral; reading 32-bit contents of the data location of the peripheral; multiplexing the received 16-bit data with the read 32-bit contents; and writing a new 32-bit word, including the modified sixteen bits and an unmodified sixteen bits, to the data location of the peripheral, without any intervention from the DSP subsequent to receiving the write transaction.

Performing an N-bit write access to an M&#xd7;N-bit-only peripheral

A computer is provided having a bus interface unit coupled between a processor bus, a peripheral bus, and a memory bus. The bus interface unit includes a processor controller linked to the processor bus for controlling the transfer of cycles from the processor to the peripheral bus and memory bus. Those cycles are initially forwarded as a request, whereby the processor controller includes a memory request queue separate from a peripheral request queue. Requests from the memory and peripheral request queues can be de-queued concurrently to the memory and peripheral buses. This enhances throughput of read and write requests; however, proper ordering of data returned as a result of read requests and data transferred as a result of write requests must be ensured. An in-order queue is also present in the processor controller which records the order in which the requests are dispatched to the peripheral and memory buses from the peripheral and memory request queues. Data ensuing from the request can be re-ordered and presented to the destination based on the current pointer position within the in-order queue. Thus, the in-order queue keeps track of the order in which data is transferred across the processor bus consistent with the order in which the previous requests were transferred.

System and method for concurrently requesting input/output and memory address space while maintaining order of data sent and returned therefrom

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Pembroke Pines, FL, United States of America

Clarence Coffee