Freescale Semiconductor,inc.

Clarance J Tracy

Thomas Andre

Nicholas David Rizzo

Saied N Tehrani

Mark A Durlam

Bradley Neal Engel

Joseph J Nahas

Gregory W Grynkewich

Brian R Butcher

Bradley J Garni

Mark F Deherrera

An MRAM architecture is provided that reduces the number of isolation transistors. The MRAM architecture includes magnetoresistive memory cells that are electrically coupled to form a ganged memory cell. The magnetoresistive memory cells of the ganged memory cell are formed with Magnetic Tunnel Junctions (MTJs) and formed without isolation devices, such as isolation transistors, and a programming line and a bit line are adjacent to each of the magnetoresistive memory cells. Preferably, the magnetoresistive memory cells of the ganged memory cell only include MTJs, and a programming line and a bit line are adjacent to each of the magnetoresistive memory cells.

MRAM architecture

Growing community of inventors

Tempe, AZ, United States of America

Clarance J Tracy